Digital_sample_and_hold_circuit

Published:2009/7/21 23:06:00 Author:Jessie | From:SeekIC

Digital sample-and-hold circuit. When a strobe input is applied the 8240/8250 is first reset, then triggered through the small RC network at pin 11, which delays the strobe signal. The strobe also sets the flip-flop, which in turn enables the counter via pin 14. The op amp goes to the high state and begins to countdown at a rate set by the counter time base. When the op amp output reaches the analog input to be sampled the comparator switches, resetting the flip-flop and stops the count. The op amp output will accurately hold the sampled value until the next strobe pulse is applied. If the time base here is used the maximum acquisition time would be 256 (8240, 100 for the 8250) times 0.01 ms, or 2.6 ms (courtesy Intersil, Inc.).



Reprinted Url Of This Article:
http://www.seekic.com/circuit_diagram/Electrical_Equipment_Circuit/Digital_sample_and_hold_circuit.html

Print this Page | Comments | Reading(3)