VIDEO_TITLER

Published:2009/6/24 21:38:00 Author:May | From:SeekIC

The figure shows the schematic of the video titler circuit. The power-on reset function is generated by IC7, a Maxim MAX699 reset, and watchdog pulse generator. That device supplies a reset pulse of 140 to 500 ms at power-up. This is accomplished with some external parts, as well as the OSD controller in IC1. First, the horizontal and vertical sync from the composite video input is detected by IC2, which is set for NTSC specification horizontal and vertical synchronization timing via resistor R4.The detected horizontal and vertical sync is fed to IC1. The OSC controller in IC1 uses these sig-nals to internally synchronize the overlay text to the incoming video. The frequency of the dot clock is controlled by components L1, C5, and C6. Text is overlaid by video multiplexer IC5, which is con-trolled by IC1.The overlay character outline and intensity are controlled via solid-state potentiometers, allow-ing the microcontroller to control the position of their wipers and store the settings in an onboard EEPROM. The microcontroller's OSC logic controls the multiplexer timing from the BF (IC1, pin 30) and VIDCTL (IC1, pin 25) signals. The BF signal switches the video multiplexer between character and character-outline video, and VIDCTL switches the multiplexer between the input video and the overlay video from IC1. The dc levels from IC3 and IC4 set the character and outline intensity, and these levels are fed to video multiplexer IC5.The video titler can store and recall text from EEPROM IC6, which has enough capacity to store one overlay screen and other required data, such as network address, horizontal and vertical overlay fine position, and type of interface.The RS-232 interface is provided by a MAX202 transceiver. The RS-485 interface is provided by an LTC485 transceiver that provides both transmit and receive functions. The keyboard interface is basically a direct connection to the microprocessor.



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