PLL_LOCK_DETECTOR

Published:2009/7/13 3:46:00 Author:May | From:SeekIC

When the loop is locked, the waveforms at pins 1 and 2 of CD4046B are almost identical, differing only in polarity. This holds the output of the NOR gate low. When the loop is not locked, the output of the NOR gate is a series of pulses. This charges the 0.047-μF capacitor, and causes a low output from the CMOS buffer.



Reprinted Url Of This Article:
http://www.seekic.com/circuit_diagram/Measuring_and_Test_Circuit/PLL_LOCK_DETECTOR.html

Print this Page | Comments | Reading(3)