VCO

Published:2009/7/9 4:08:00 Author:May | From:SeekIC

At startup, the voltage in the trigger input at pin 2 is less than the trigger level voltage, 1/3 VDD, causing the timer to be triggered via pin 2. The output of the timer at pin 3 becomes high, allowing capacitor Ct to charge very rapidly through diode D1 and resistor R1.When capacitor Ct charges to the upper threshold voltage 2/3 VDD, the flip-flop is reset, the output at pin 3 decreases, and capacitor Ct discharges through the current mirror, TL011. When the voltage at pin 2 reaches 1/3 VDD, the lower threshold or trigger level, the timer triggers again and the cycle is repeated.



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