SCANNING_ASCI_NECODER

Published:2009/7/10 22:10:00 Author:May | From:SeekIC

Converts key action into composite parallel ASCLL code. Circuit includes debouncing and two-key rollover. Two 4001 quad two-input NOR gate sections form 50-kHz clock that is gated. When clock is allowed to run, two cascaded 4520 binary counters are driven for continuous cycling through all their counts. Slower counter pro-duces 1-of-8 decoded output for 4051 1-of-8 switch. Faster counter drives second switch that monitors sequential rows of characters.When key is pressed, output from +5Vthrough both selectors stops gated oscillator and holds count. Resulting ASCll output is then routed to external output logic for control and shift operations. When key is released, scanning resumes and continues until new key is pressed.If second key is pressed before first is released, nothing happens until first key is released.Scanning then resumes and stops at second key location, to give two-key rollover permitting faster typing with minimum error.-D. Lancaster, CMOS Cookbook, Howard W. Sams, Indianapolis, IN, 1977, p 358-359.



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