54ABT16500

* Combines D-Type latches and D-Type flip-flops for
   operation in transparent, latched, or clocked mode
* Flow-through architecture optimizes PCB layout
* Guaranteed latch-up protection
* High impedance glitch free bus loading during entire
   power up and power down cycle
* Non-destructive hot insertion capability
* Standard Microcircuit Drawing (SMD) 5962-9687001

These 18-bit universal bus transceivers 54ABT16500 combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the 54ABT16500 operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A bus data is stored in the latch/flip-flop on the high-to-low transition of CLKAB. Output-enable OEAB is active-high. When OEAB is high, the outputs of 54ABT16500 are active. When OEAB is low, the outputs are in the high-impedance state.

Data flow of 54ABT16500 for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKAB. The output enables are complementary (OEBA is active high and OEBA is active low).

To ensure the high-impedance state during power up or power down, OE of 54ABT16500 should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.