78P7200

Features:

• Single chip transmit and receive interface for STS-1 (51.84 Mbit/s), E3 (34.368 Mbit/s) or DS3 (44.736 Mbit/s) applications
• On-chip Receive Equalizer
• Unique clock recovery circuit, requires no crystals, tuned components or external clock
• Selectable transmit line buildout (LBO) to accommodate shorter line lengths
• Compliant with ANSI T1.102-1993, Bellcore TR-NWT-000499 and GR-253-CORE, ITU-T G.703 and G.823_1991
• Low-level input signal indication
• Available in a 28 PLCC surface mount package
• -40°C to +85°C operating range


Pinout




Specifications

PARAMETER	RATING
Positive 5V supply: TVcc, RVcc, DVcc	6V
Storage temperature	-65 to 150 °C
Soldering Temperature (10 sec.)	260 °C
Ambient Operating Temperature, TA	-40 to +85°C
Pin Ratings: LOUT+, LOUT-	Vcc -2 to Vcc +2V
LIN+, LIN-, TPOS, TNEG, TCLK, LBO, RFO, LF2, LF1, OPT!, OPT@ Pins	-0.3 to Vcc +0.3V
RPOS, RNEG, RCLK, LOWSIG Pins -0.3 to Vcc +0.3V or +12 mA	-0.3 to Vcc +0.3V or +12 mA

Description

The 78P7200 is a line interface transceiver IC intended for STS-1 (51.84 Mbit/s), DS3 (44.736 Mbit/s) and E3 (34.368 Mbit/s) applications. The receiver has a very wide dynamic range and is designed to accept either HDB3 or B3ZS-encoded Alternate-Mark Inversion (AMI) inputs; it provides CMOS logic level clock, positive data, negative data and low-level signal detector outputs. An on-chip equalizer of the 78P7200 improves the intersymbol interference tolerance on the receive path. The transmitter converts CMOS logic level clock, positive data and negative data input signals into AMI pulses of the appropriate shape for transmission. A line buildout (LBO) equalizer may be selected to shape the outgoing pulses for shorter line lengths. The 78P7200 requires a single 5 volt supply and is available in a surface mount package.