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Part Number:
A29040A
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Description：
The A29040A is a 5.0 volt-only Flash memory organized as 524,288 bytes of 8 bits eac

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General Description

The A29040A is a 5.0 volt-only Flash memory organized as 524,288 bytes of 8 bits each. The 512 Kbytes of data are further divided into eight sectors of 64 Kbytes each for flexible sector erase capability. The 8 bits of data appear on I/O0 - I/O7 while the addresses are input on A0 to A18. The A29040A is offered in 32-pin PLCC, TSOP, and PDIP packages. This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply. Additional 12.0 volt VPP is not required for in-system write or erase operations. However, the A29040A can also be programmed in standard EPROM programmers. The A29040A has a second toggle bit, I/O2, to indicate whether the addressed sector is being selected for erase, and also offers the ability to program in the Erase Suspend mode.

The standard A29040A offers access times of 55, 70 and 90 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE ), write enable (WE ) and output enable (OE ) controls.

The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.

Maximum Ratings

Ambient Operating Temperature . . . . -55°C to + 125°C
Storage Temperature . . . . . . . . . . . . . .-65°C to + 125°C
VCC to Ground . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to 7.0V
Output Voltage (Note 1) . . . . . . . . . . . . . . .. -2.0V to 7.0V
A9 & OE (Note 2) . . . . . . . . . . . . . . . . . . . . -2.0V to 12.5V
All other pins (Note 1) . . . . . . . . . . . . . . . . . -2.0V to 7.0V
Output Short Circuit Current (Note 3) . . . . . . . . . . 200mA

Features

5.0V ± 10% for read and write operations
Access times:
- 55/70/90 (max.)
Current:
- 20 mA typical active read current
- 30 mA typical program/erase current
- 1 mA typical CMOS standby
Flexible sector architecture
- 8 uniform sectors of 64 Kbyte each
- Any combination of sectors can be erased
- Supports full chip erase
- Sector protection:
A hardware method of protecting sectors to prevent
any inadvertent program or erase operations within
that sector
Embedded Erase Algorithms
- Embedded Erase algorithm will automatically erase
the entire chip or any combination of designated
sectors and verify the erased sectors
- Embedded Program algorithm automatically writes
and verifies bytes at specified addresses
Typical 100,000 program/erase cycles per sector
20-year data retention at 125°C
- Reliable operation for the life of the system
Compatible with JEDEC-standards
- Pinout and software compatible with single-power-
supply Flash memory standard
- Superior inadvertent write protection
Data Polling and toggle bits
- Provides a software method of detecting completion
of program or erase operations
Erase Suspend/Erase Resume
- Suspends a sector erase operation to read data from,
or program data to, a non-erasing sector, then
resumes the erase operation
Package options
- 32-pin P-DIP, PLCC, or TSOP (Forward type)