Purchase ACT-D1M96S, In-stock ACT-D1M96S From SeekIC.
Part Number: ACT-D1M96S
Description: The ACT-D1M96S device is a high-speed 96Mbit synchronous dynamic random access memory (SDRAM) organize...
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ACT-D1M96S
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DataSheet
General Description
ACT-D1M96S General Description
The ACT-D1M96S device is a high-speed 96Mbit synchronous dynamic random access memory (SDRAM) organized as 2 independent 512K X 48 X 2 banks. All inputs and outputs of the ACT-D1M96S are compatible with the LVTTL interface. All inputs and outputs are synchronized with the CLK input to simplify system design and enhance use with high-speed microprocessors and caches.
ACT-D1M96S Maximum Ratings
|
Symbol |
Rating |
Range |
Units |
|
VCC |
Supply Voltage |
-0.5 to 4.6 |
V |
|
VCCQ |
Supply Voltage range for output drivers |
-0.5 to 4.6 |
V |
|
VRANGE |
Voltage range on any pin with respect to VSS |
-0.5 to 4.6 |
V |
|
TBIAS |
Case Temperature under Bias2 |
-55 to +125 |
°C |
|
TSTG |
Storage Temperature |
-65 to +150 |
°C |
|
ISHORT |
Short-Circuit Output Current |
50 |
mA |
|
PW |
Power Dissipation |
4.2 |
W |
ACT-D1M96S Features
6 Low Power Micron 1M X 16 Synchronous Dynamic
Random Access Memory Chips in one MCM
User Configureable as "2" Independent 512K X 48 X 2 Banks
High-Speed, Low-Noise, Low-Voltage TTL (LVTTL) Interface
3.3-V Power Supply (±10% Tolerance)
Separate Logic and Output Driver Power Pins
Two Banks for On-Chip Interleaving (Gapless Accesses)
Up to 50-MHz Data Rates
CAS Latency (CL) Programmable to 2 Cycles From Column-Address Entry
Burst Length Programmable to 4 or 8
Pipeline Architecture
Cycle-by-Cycle DQ-Bus Write Mask Capability With Upper and Lower Byte Control
Chip Select and Clock Enable for Enhanced-System Interfacing
Serial Burst Sequence
Auto-Refresh
4K Refresh (Total for Both Banks)
200-lead CQFP, cavity-up package
Random Access Memory Chips in one MCM
User Configureable as "2" Independent 512K X 48 X 2 Banks
High-Speed, Low-Noise, Low-Voltage TTL (LVTTL) Interface
3.3-V Power Supply (±10% Tolerance)
Separate Logic and Output Driver Power Pins
Two Banks for On-Chip Interleaving (Gapless Accesses)
Up to 50-MHz Data Rates
CAS Latency (CL) Programmable to 2 Cycles From Column-Address Entry
Burst Length Programmable to 4 or 8
Pipeline Architecture
Cycle-by-Cycle DQ-Bus Write Mask Capability With Upper and Lower Byte Control
Chip Select and Clock Enable for Enhanced-System Interfacing
Serial Burst Sequence
Auto-Refresh
4K Refresh (Total for Both Banks)
200-lead CQFP, cavity-up package
ACT-D1M96S
PDF/DataSheet Download
- Datasheet: ACT-D1M96S
- File Size: 108076 KB
- Manufacturer: AEROFLEX [Aeroflex Circuit Technology]
- Click here to Download
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