ACT-F128K32

The ACT- F128K32 is a hig speed, 4 megabit CMOS flash multichip module (MCM) designed for full temperature range military, space, or high reliability applications.

The MCM can be organized as a 128K x 32 bits, 256K x 16 bits or 512K x 8 bits device and is input TTL and output CMOS compatible. The command register is written by bringing to a logic low level (VIL), WE is low and  OE is at while  CEIH). Reading islogic high level (Vaccomplished by chip En able) and Output Enable (OE)(CEbeing logically active, seeFigure 9. Access time grades of60ns, 70ns, 90ns, 120ns and150ns maximum are standard.

The ACT¨CF128K32 ipackaged in a hermetically sealed co-fired ceramic 66 pin, 1.08" sq PGA or a 68 lead,  .88" sq  Ceramic Gull Wing CQFP package for operation over the temperature range of -55 to +125 a military environment.  
Each flash memory die is organized as 128KX8 bits and is designed to be programmed in-system with the standard PP is system 5.0V Vcc supply.  A 12.0V V not required for write or erase operations.

The MCM can also be reprogrammed with standard EPROM programmers (with the proper ocket).The standard ACT-F128K32 offers access times between 60ns and 150ns, allowing operation of high-speed microprocessors without wait states.  To eliminate bus contention, the device has ) and write enable separate chip enable (CE ).  The ACT-F128K32 is command set (WE compatible with JEDEC standard 1 Mbit EEPROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations.

Reading data out of the device is similar to reading from 12.0V Flash or EPROM devices. The ACT-F128K32 is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in less than 0.3 second. Erase is accomplished by executing the erase command sequence.

This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array, (if it is not already programmed before) executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

Each die in the module or any individual sector of the die is typically erased and verified in 1.3 seconds (if already completely preprogrammed).

Each die also features a sector erase architecture. The sector mode allows for 16K byte blocks of memory to be erased and reprogrammed without affecting other blocks. The ACT-F128K32 is erased when shipped from the factory.
The device features single 5.0V power supply operation for both read and write functions. lnternally generated and regulated voltages are provided for the CC program and erase operations. A low V detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by  Data Polling of D7 or by the Toggle Bit feature on D6. Once the end of a program or erase cycle has been completed,-+ the device internally resets to the read mode.

 All bits of each die, or all bits within a sector of a die, are erased via Fowler-Nordhiem tunneling. Bytes are programmed one byte at a time by hot electron injection.

DESC Standard Military Drawing (SMD) numbers are released.