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Part Number: AD6624

 

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Description: The AD6624 is a four-channel (quad) digital receive signal processor (RSP) with four cascaded signal-p...


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AD6624 General Description


The AD6624 is a four-channel (quad) digital receive signal processor (RSP) with four cascaded signal-processing elements:a frequency translator, two fixed-coefficient decimating filters,and a programmable coefficient-decimating filter.

The AD6624 is part of Analog Devices' SoftCell® multicarrier transceiver chipset designed for compatibility with Analog Devices' family of high sample rate IF sampling ADCs (AD6640/AD6644 12- and 14-bit). The SoftCell receiver comprises a digital receiver capable of digitizing an entire spectrum of carriers and digitally selecting the carrier of interest for tuning and channel selection. This architecture eliminates redundant radios in wireless base station applications.

High dynamic range decimation filters offer a wide range of decimation rates. The RAM-based architecture allows easy
reconfiguration for multimode applications.

The decimating filters remove unwanted signals and noise from the channel of interest. When the channel of interest occupies less bandwidth than the input signal, this rejection of out-of-band noise is called "processing gain." By using large decimation factors, this "processing gain" can improve the SNR of the ADC by 30 dB or more. In addition, the programmable RAM Coefficient filter allows antialiasing, matched filtering, and static equalization functions to be combined in a single, costeffective filter.

The AD6624 is compatible with standard ADC converters such as the AD664x, AD9042, AD943x and the AD922x families of data converters. The AD6624 is also compatible with the AD6600 Diversity ADC, providing a cost and size reduction path.

AD6624 Maximum Ratings

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
Input Voltage . . . . . . . . . . . . 0.3 V to +5.3 V (5 V Tolerant)
Output Voltage Swing . . . . . . . . . . 0.3 V to VDDIO + 0.3 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . 125°C
Storage Temperature Range . . . . . . . . . .65°C to +150°C
Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . 280°C

*Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

AD6624 Features

·80 MSPS Wide Band Inputs (14 Linear Bits Plus 3 RSSI)
·Dual High-Speed Data Input Ports
·Four Independent Digital Receivers in Single Package
·Digital Resampling for Noninteger Decimation Rates
·Programmable Decimating FIR Filters
·Programmable Attenuator Control for Clip Prevention and External Gain Ranging via Level Indicator
·Flexible Control for Multicarrier and Phased Array
·3.3 V I/O, 2.5 V CMOS Core
·User Configurable Built-In Self-Test (BIST) Capability
·JTAG Boundary Scan

AD6624 Typical Application

·Multicarrier, Multimode Digital Receivers GSM, IS136,EDGE, PHS, IS95
·Micro and Pico Cell Systems
·Wireless Local Loop
·Smart Antenna Systems
·Software Radios
·In-Building Wireless Telephony

AD6624 Connection Diagram

AD6624  Connection Diagram

AD6624 datasheet

AD6624
PDF/DataSheet Download

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