AD6654

The AD6654 is a mixed-signal IF-to-baseband receiver consisting of a 14-bit, 92.16 MSPS analog-to-digital converter (ADC) and a 4-/6-channel, multimode digital down-converter (DDC) capable of processing up to six WCDMA (wideband code division multiple access) channels. The AD6654 has been optimized for the demanding filtering requirements of wide-band standards such as CDMA2000, UMTS, and TD-SCDMA, but is flexible enough to support wider standards such as WiMAX. It is typically used as part of a radio system that digitally demodulates and filters IF sampled signals.

The ADC stage features a high performance track-and-hold input amplifier (T/H), integrated voltage reference, and 14-bit sampling resolution. Input signals up to 200 MHz can be accurately digitized at encode rates up to 92.16 MSPS. The ADC data outputs are internally routed directly into the DDC inputs, where down-conversion, decimation and digital filtering are performed. An overrange (OVR) output bit provides indication of excessive ADC input levels. An ADC data-ready (DR) output bit provides a synchronized clock for the integrated DDC.

Data from the ADC is evaluated for peak or mean power in the input stage of the DDC, and the result is available to the user via control register access. The DDC input stage also outputs 3-bit level-indicator data (EXP) bits that can be used to control the gain of the external DVGA in 6 dB steps (up to 48 dB) to optimize signal amplitude into the ADC input.

The DDC stage has the following signal processing stages: six WCDMA-ready channels, each consisting of a frequency translator, a fifth-order cascaded integrated comb filter, two sets of cascaded fixed coefficient FIR and half-band filters, three cascaded programmable sum of product FIR filters, an interpolating half-band filter (IHB), and a digital automatic gain control (AGC) block. Multiple modes are supported for clocking data out of the chip. Programming is accomplished via serial or microport interfaces.

Frequency translation is accomplished with a 32-bit complex numerically controlled oscillator (NCO). The NCO has greater than 110 dBc SDFR. This stage translates a real input signal from an intermediate frequency (IF) to a baseband complex digital output. Phase and amplitude dither can be enabled on-chip to improve spurious performance of the NCO. A 16-bit phase-offset word is available to create a known phase relation-ship between multiple AD6654 chips or channels. The NCO can also be bypassed.

Following frequency translation is a fifth-order CIC filter with a programmable decimation between 1 and 32. This filter is used to efficiently lower the sample rate, while providing sufficient alias rejection at frequencies at higher offsets from the signal of interest.

Following the CIC5 are two sets of filters. Each filter set includes a nondecimating FIR filter and a decimate-by-2 half-band filter. The FIR1 filter provides about 30 dB of rejection, while the HB1 provides about 77 dB of rejection. These two sets of filters can be used together to achieve a 107 dB stop-band alias rejection, or they can be individually bypassed to save power.

The FIR2 filter provides about 30 dB of rejection, while the HB2 filter provides about 65 dB of rejection. The filters can be used together to achieve more than 95 dB stop-band alias rejection, or they can be individually bypassed to save power. FIR1 and HB1 filters can run at the maximum ADC data port rate. In contrast, FIR2 and HB2 can run with a maximum input rate of 75 MSPS (input rate to FIR2 and HB2 filters).

The programmable filtering is divided into three cascaded RAM coefficient filters (RCFs) for flexible and power-efficient filtering. The first filter in the cascade is the MRCF, consisting of a programmable nondecimating FIR. It is followed by programmable FIR filters (DRCF) with decimation from 1 to 16. They can be used either together to provide high rejection filters, or independently to save power. The maximum input rate to the MRCF is one-fourth the PLL clock rate.

The CRCF (Channel RCF) is the last programmable FIR filter with programmable decimation from 1 to 16. It is typically used to meet the spectral mask requirements for the air standard of interest. This could be an RRC, antialiasing filter or any other real data filter. Decimation in preceding blocks is used to keep the input rate of this stage as low as possible for the best filter performance.

The last filter stage in the chain is an interpolate-by-2 half-band filter, which is used to up-sample the CRCF output to produce higher output oversampling. Signal rejection requirements for this stage are relaxed, because preceding filters have already filtered the blockers and adjacent carriers.

The DDC input port of the AD6654 has its own clock input used for latching the input data, as well as for providing the input for an onboard PLL clock multiplier. The output of the PLL clock is used for processing all filters and processing blocks beyond the data router following CIC filter. The PLL clock can be programmed to have a maximum clock rate of 200 MHz. Typically, the DDC input clock is driven directly from the integrated ADC's data-ready (DR) output to ensure proper synchronization.

A data routing block is used to distribute data from the CICs to the various channel filters. This block allows multiple back-end filter chains to work together to process high bandwidth signals or to make even sharper filter transitions than a single channe can perform. It can also allow complex filtering operations to be achieved in the programmable filters.

The digital AGC provides the user with scaled digital outputs based on the rms level of the signal present at the output of the digital filters. The user can set the requested level and time constant of the AGC loop for optimum performance of the postprocessor. This is a critical function in the base station for CDMA application, where the power level must be well controlled going into the RAKE receivers. It has programmable clipping and rounding control to provide different output resolutions.

The overall filter response for the AD6654 is the composite of all the combined filter stages. Each successive filter stage is capable of narrower transition bandwidths, but requires a greater number of CLK cycles to calculate the output. The AD6654 features a fractional clock multiplier that uses the ADC clock (which is slower than the DDC's processing speed) to produce a DDC master clock up to 200 MHz. This feature allows fractional multiplication of the input clock to allow the DDC to function at maximum speed while maintaining edge identity to the ADC clock.

More decimation in the first filter stage minimizes overall power consumption. Data from the device is interfaced to a DSP/FPGA/baseband processor via high speed parallel ports (preferred), or a DSP-compatible microprocessor interface.

The AD6654 is available in 4-channel and 6-channel versions. The primary focus of the data sheet is on the 6-channel part. The only difference between the 6-channel and 4-channel devices is that, on the 4-channel version, Channel 4 and Channel 5 are not available (see Figure 1). The 4-channel device has the same DDC input port features, output ports, and memory map as the 6-channel device. On the 4-channel version, the memory map section for Channel 4 and Channel 5 can be programmed and read back, but the two extra channels are disabled internally.