Features: Single 3 V or 5 V Supply14-Bit DAC Resolution and Input Data Width32 MSPS Input Data Rate at 5 V13.5 MHz Reconstruction Bandwidth12 ENOBS @ 1 MHz77 dBc SFDR @ 5 MHz43 Interpolation Filter69 dB Image Rejection84% Passband to Nyquist Ratio0.002 dB Passband Ripple23 3/4 Cycle LatencyInterna...
AD9774: Features: Single 3 V or 5 V Supply14-Bit DAC Resolution and Input Data Width32 MSPS Input Data Rate at 5 V13.5 MHz Reconstruction Bandwidth12 ENOBS @ 1 MHz77 dBc SFDR @ 5 MHz43 Interpolation Filter6...
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Parameter | With Respectto | Min | Max | Units |
AVDD DVDD PLLVDD ACOM PLLCOM PLLCOM AVDD PLLVDD PLLVDD CLKIN, CLK4` IN SLEEP, SNOOZE Digital Inputs PLL DIVIDE, LPF PLLLOCK VCO IN/EXT IOUTA/IOUTB REFIO, FSADJ FSADJ ICOMP REFCOM Junction Temperatur Storage Temperature Lead Temperature (10 sec) |
ACOM DCOM PLLCOM DCOM ACOM DCOM DVDD DVDD AVDD DVDD DCOM DCOM ACOM ACOM ACOM ACOM ACOM ACOM ACOM ACOM |
0.3 0.3 0.3 0.3 0.3 0.3 6.5 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 65 |
+6.5 +6.5 +6.5 +0.3 +0.3 +0.3 +6.5 +6.5 +6.5 +6.5 DVDD + 0.3 DVDD + 0.3 PLLVDD + 0. PLLVDD + 0. PLLVDD + 0. AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 +0.3 +150 +150 +300 |
V |
The AD9774 is a single supply, oversampling, 14-bit digital-to-analog converter (DAC) optimized for waveform reconstruction applications requiring exceptional dynamic range. Manufac-
tured on an advanced CMOS process, it integrates a complete,low distortion 14-bit DAC with a 4· digital interpolation filter and clock multiplier. The two-stage, 4· digital interpolation
filter provides more than a six-fold reduction in the complexity of the analog reconstruction-filter. It does so by multiplying the input data rate by a factor of four while simultaneously suppressing the original inband images by more than 69 dB. The on-chip clock multiplier provides all the necessary clocks. The AD9774 can reconstruct full-scale waveforms having bandwidths as high as 13.5 MHz when operating at an input data rate of 32 MSPS and a DAC output rate of 128 MSPS.
The 14-bit DAC provides differential current outputs to support differential or single-ended applications. A segmented current source architecture is combined with a proprietary switching tech-nique to reduce spurious components and enhance dynamic per-formance. Matching between the two current outputs ensures enhanced dynamic performance in a differential output configura-tion. The differential current outputs may be fed into a transformer or tied directly to an output resistor to provide two complementary,single-ended voltage outputs. A differential op amp topology can also be used to obtain a single-ended output voltage. The output voltage compliance range is nominally 1.25 V.