ADF4110

Features:

ADF4110: 550 MHz
ADF4111: 1.2 GHz
ADF4112: 3.0 GHz
ADF4113: 4.0 GHz
2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (VP) Allows Extended Tuning Voltage in 3 V Systems
Programmable Dual Modulus Prescaler 8/9, 16/17, 32/33, 64/65
Programmable Charge Pump Currents
Programmable Antibacklash Pulsewidth
3-Wire Serial Interface
Analog and Digital Lock Detect
Hardware and Software Power-Down Mode




Application

Base Stations for Wireless Radio (GSM, PCS, DCS,CDMA, WCDMA)
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANS
Communications Test Equipment
CATV Equipment




Pinout








Specifications



AV_DD to GND³. . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V
AV_DD to DVDD . . . . . . . . . . . . . . . . . . . . . .0.3 V to +0.3 V
V_P to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .0.3 V to +7 V
V_P to AVDD . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . . . 0.3 V to V_DD + 0.3 V
Analog I/O Voltage to GND . . . . . . . . .0.3 V to V_P + 0.3 V
REFIN, RFINA, RFINB to GND . . . . . . 0.3 V to V_DD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . 40°C to +85°C
Storage Temperature Range . . . . . . . . . 65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
TSSOP _JA Thermal Impedance . . . . . . . . . . . . .150.4°C/W
CSP _JA Thermal Impedance (Paddle Soldered) . . 122°C/W




Description

The ADF4110 family of frequency synthesizers can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. ADF4110 consists of a low-noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider,
programmable A and B counters and a dual-modulus prescaler (P/P+1). The A (6-bit) and B (13-bit) counters, in conjunction with the dual modulus prescaler (P/P+1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R Counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (Phase-Locked Loop) can be implemented if the synthesizer is used with an external loop filter and VCO (Voltage Controlled Oscillator).