ADF4206

Features:

ADF4206: 550 MHz/550 MHz
ADF4207: 1.1 GHz/1.1 GHz
ADF4208: 2.0 GHz/1.1 GHz
2.7 V to 5.5 V Power Supply
Selectable Charge Pump Supply (VP) Allows Extended Tuning Voltage in 3 V Systems
Selectable Charge Pump Currents
On-Chip Oscillator Circuit
Selectable Dual Modulus Prescaler
RF2: 32/33 or 64/65
RF1: 32/33 or 64/65
3-Wire Serial Interface
Power-Down Mode




Application

Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Base Stations for Wireless Radio (GSM, PCS, DCS,CDMA, WCDMA)
Wireless LANS
Communications Test Equipment
CATV Equipment




Pinout








Specifications

V_DD1 to GND³. . . . . . . . . . . . . . . . . . . . . . . .0.3 V to +7 V
V_DD1 to VDD2 . . . . . . . . . . . . . . . . . . . . . .0.3 V to +0.3 V
V_P1, V_P2 to GND . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V
V_P1, V_P2 to V_DD1 . . . . . . . . . . . . . . . . . . .0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . 0.3 V to DV_DD + 0.3 V
Analog I/O Voltage to GND . . . . . . . . 0.3 V to V_P + 0.3 V
OSC_IN, OSC_OUT, RF1_IN (A, B),
RF2_IN (A, B) to GND . . . . . . . . . . . . 0.3 V to V_DD + 0.3 V
RFINA to RFINB (RF1, RF2) . . . . . . . . . . . . . . . . . ±320 mV
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . 40°C to +85°C
Storage Temperature Range . . . . . . . . .65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . 150°C
TSSOP JA Thermal Impedance . . . . . . . . . . . . 150.4°C/W






Description

The ADF4206 family of dual frequency synthesizers can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. ADF4206 consists of a low-noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, programmable A and B counters and a dualmodulus prescaler (P/P + 1). The A (6-bit) and B (11-bit) counters, in conjunction with the dual modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R Counter), allows selectable REFIN frequencies at the PFD input. The on-chip oscillator circuitry allows the reference input to be derived from crystal oscillators. A complete PLL (Phase-Locked Loop) can be implemented if the synthesizers are used with an external loop filter and VCOs (Voltage Controlled Oscillators). Control of all the on-chip registers is via a simple 3-wire interface. ADF4206 operates with a power supply ranging from 2.7 V to 5.5 V and can be powered down when not in use.