ADF4210

Features:

ADF4210: 550 MHz/1.2 GHz
ADF4211: 550 MHz/2.0 GHz
ADF4212: 1.0 GHz/2.7 GHz
ADF4213: 1.0 GHz/3 GHz
2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (VP) Allows Extended Tuning Voltage in 3 V Systems
Programmable Dual Modulus Prescaler RF and IF: 8/9, 16/17, 32/33, 64/65
Programmable Charge Pump Currents
3-Wire Serial Interface
Analog and Digital Lock Detect
Fastlock Mode
Power-Down Mode


Application

Base Stations for Wireless Radio (GSM, PCS, DCS,CDMA, WCDMA)
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANS
Communications Test Equipment
CATV Equipment


Pinout




Specifications

V_DD1 to GND³. . . . . . . . . . . . . . . . . . . . . . . .  0.3 V to +7 V
V_DD1 to VDD2  . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +0.3 V
V_P1, V_P2 to GND  . . . . . . . . . . . . . . . . . . . . . .0.3 V to +7 V
V_P1, V_P2 to VDD1  . . . . . . . . . . . . . . . . . . . 0.3 V to +5.5 V
Digital I/O Voltage to GND  . . . . . .   0.3 V to DV_DD + 0.3 V
Analog I/O Voltage to GND  . . . . . . . . . 0.3 V to V_P + 0.3 V
REF_IN, RF_INA, RF_INB,
IF_INA, IF_INB to GND  . . . . . . . . . . . .   0.3 V to V_DD + 0.3 V
Operating Temperature Range
Industrial (B Version)  . . . . . . . . . . . . . . . . 40°C to +85°C
Storage Temperature Range  . . . . . . . . . 65°C to +150°C
Maximum Junction Temperature  . . . . . . . . . . . . . . .  150°C
TSSOP _JA Thermal Impedance  . . . . . . . . . . . . 150.4°C/W
CSP _JA (Paddle Soldered)  . . . . . . . . . . . . . . . . . 122°C/W


Description

The ADF4210/ADF4211/ADF4212/ADF4213 is a dual frequency synthesizer that can be used to implement local oscillators (LO) in the upconversion and downconversion sections of wireless receivers and transmitters. They can provide the LO for both the RF and IF sections. ADF4210/ADF4211/ADF4212/ADF4213  consist of a low-noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, programmable A and B Counters and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B (12-bit) counters, in conjunction with the dual modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R Counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (Phase- Locked Loop) can be implemented if the synthesizer is used with an external loop filter and VCO (Voltage Controlled Oscillators).

Control of all the on-chip registers is via a simple 3-wire interface.ADF4210/ADF4211/ADF4212/ADF4213 operate with a  power supply ranging from 2.7 V to 5 V and can be powered down when not in use.