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Part Number: ATF1504AE(L)

 

 

 

 

Description: Beginning with the introduction of the 100% connected ATF1500 with 32 enhanced macrocells in 1996, Atm...


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ATF1504AE(L) General Description


Beginning with the introduction of the 100% connected ATF1500 with 32 enhanced macrocells in 1996, Atmel's CPLD products have delivered extra IO connectivity and logic reusability. Atmel's commitment to efficient, flexible architecture has continued with the current Atmel ATF15xx Family of industry standard, pin-compatible CPLDs. Atmel's Logic Doubling architecture consists of wider fan-in, additional routing and clock options, combined with sophisticated, proprietary device fitters, extend CPLD place and route efficiency. Atmel enhanced macrocell includes double independent buried feedback that allows designers to pack more logic (particularly shifters and latches) into a smaller CPLD or leave spare room for later revisions. The Atmel ATF15xx family delivers enhanced functionality and flexibility with no additional design effort and is highly cost effective.

The Atmel ATF15xx Family includes all popular configurations and speeds.

ATF1504AE(L) Maximum Ratings

Ambient Temperature Under Bias....................................-65°C

Storage Temperature.....................................-65°C to +150°C

Junction Temperature..............................................150°C(MAX)

Voltage on Any Pin with
Respect to Ground........................................-2.0V to +5.75V(1)

Voltage on Input Pins
with Respect to Ground
During Programming......................................-2.0V to +14.0V(1)

Programming Voltage with
Respect to Ground........................................-2.0V to +14.0V(1)

DC Output Current per Pin..................................-25 to +25 mA
 

ATF1504AE(L) Features

2nd Generation EE Complex Programmable Logic Devices
   3.0V to 3.6V Operating Range with 5V Tolerant I/Os
   32 - 512 Macrocells with Enhanced Features
   Pin-compatible with Industry-standard Devices
   Speeds to 4.5 ns Maximum Pin-to-pin Delay
   Registered Operation to 225 MHz
Enhanced Macrocells with Logic Doubling™ Features
   Bury Either Register or COM while Using the Other for Output
   Dual Independent Feedback Allows Multiple Latch Functions per Macrocell
   5 Product Terms per Macrocell, Expandable to 40 per Macrocell with Cascade
Logic, Plus 15 More with Foldback Logic
   D/T/Latch Configurable Flip-flops plus Transparent Latches
   Global and/or per Macrocell Register Control Signals
   Global and/or per Macrocell Output Enable
   Programmable Output Slew Rate per Macrocell
   Programmable Output Open Collector Option per Macrocell
   Fast Registered Input from Product Term
Enhanced Connectivity
   Single Level Switch Matrix for Maximum Routing Options
   Up to 40 Inputs per Logic Block
Advanced Power Management Features
   ITD (Input Transition Detection) Available Individually on Global Clocks, Inputs and
     I/O for µA Level Standby Current on "L" versions
   Pin-controlled 1 mA Standby Mode
   Reduced-power Option per Macrocell
   Automatic Power Down of Unused Macrocells
   Programmable Pin-keeper Inputs and I/Os
Available in Commercial and Industrial Temperature Ranges
Available in All Popular Packages Including PLCC, PQFP, TQFP and BGA
EE Technology
   100% Tested
   Completely Reprogrammable
   10,000 Program/Erase Cycles
   20 Year Data Retention
   2000V ESD Protection
   200 mA Latch-up Immunity
JTAG Boundary-scan Testing Port per IEEE 1149.1-1990 and 1149.1a-1993
   Pull-up Option on JTAG Pins TMS and TDI
IEEE 1532 Compatibility for Fast In-System Programmability (ISP) via JTAG
   PCI-compliant
Security Fuse Feature

ATF1504AE(L) Connection Diagram

ATF1504AE(L)  Connection Diagram

ATF1504AE(L) datasheet

ATF10100
PDF/DataSheet Download

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