ATF1508ASL

The ATF1508AS is a high-performance, high-density complex programmable logic device(CPLD) that utilizes Atmel's proven electrically-erasable technology. With 128 logic macrocellsand up to 100 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classicPLDs. The ATF1508AS's enhanced routing switch matrices increase usable gate count andincrease odds of successful pin-locked design modifications.

The ATF1508AS has up to 96 bi-directional I/O pins and four dedicated input pins, dependingon the type of device package selected. Each dedicated pin can also serve as a global controlsignal, register clock, register reset or output enable. Each of these control signals can beselected for use individually within each macrocell.

Each of the 128 macrocells generates a buried feedback that goes to the global bus. Eachinput and I/O pin also feeds into the global bus. The switch matrix in each logic block thenselects 40 individual signals from the global bus. Each macrocell also generates a foldbacklogic term that goes to a regional bus.

Cascade logic between macrocells in the ATF1508ASallows fast, efficient generation of complex logic functions. The ATF1508AS contains eightsuchlogicchains,eachcapableofcreatingsumtermlogicwithafan-inofupto40productterms.

The ATF1508AS macrocell, shown in Figure 1, is flexible enough to support highly-complexlogic functions operating at high speed. The macrocell consists of five sections: product termsand product term select multiplexer; OR/XOR/CASCADE logic, a flip-flop, output select andenable, and logic array inputs.

Unused macrocells are automatically disabled by the compiler to decrease power consump-tion. A security fuse, when programmed, protects the contents of the ATF1508AS. Two bytes(16 bits) of User Signature are accessible to the user for purposes such as storing projectname, part number, revision or date.

The User Signature is accessible regardless of the stateof the security fuse.

The ATF1508AS device is an in-system programmable (ISP) device. It uses the industry-stan-dard 4-pin JTAG interface (IEEE Std. 1149.1), and is fullycompliant with JTAG's Boundary-scan Description Language (BSDL). ISP allows the device to be programmed without remov-ing it from the printedcircuit board. In addition to simplifying the manufacturing flow, ISP alsoallows design modifications to be made in the field via software.