C161O Selling Leads, Price trend, C161O DataSheet download, circuit diagram from SeekIC.com

Features: • High Performance 16-bit CPU with 4-Stage Pipeline 80 ns Instruction Cycle Time at 25 MHz CPU Clock 400 ns Multiplication (16 * 16 bit), 800 ns Division (32 / 16 bit) Enhanced Boolean Bit Manipulation Facilities Additional Instructions to Support HLL and Operating Systems Register...

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SeekIC No. : 004308031 Detail

C161O: Features: • High Performance 16-bit CPU with 4-Stage Pipeline 80 ns Instruction Cycle Time at 25 MHz CPU Clock 400 ns Multiplication (16 * 16 bit), 800 ns Division (32 / 16 bit) Enhanced Boole...

C161O Data Sheet

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Part Number:: C161O
Supply Ability:: 5000

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Product Details

Description

Features:

• High Performance 16-bit CPU with 4-Stage Pipeline
80 ns Instruction Cycle Time at 25 MHz CPU Clock
400 ns Multiplication (16 * 16 bit), 800 ns Division (32 / 16 bit)
Enhanced Boolean Bit Manipulation Facilities
Additional Instructions to Support HLL and Operating Systems
Register-Based Design with Multiple Variable Register Banks
Single-Cycle Context Switching Support
16 MBytes Total Linear Address Space for Code and Data
1024 Bytes On-Chip Special Function Register Area
• 16-Priority-Level Interrupt System with 20 Sources, Sample-Rate down to 40 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC)
• Clock Generation via prescaler or via direct clock input
• On-Chip Memory Modules
2 KBytes On-Chip Internal RAM (IRAM) on C161O, 1 KByte IRAM on C161K
• On-Chip Peripheral Modules
Two Multi-Functional General Purpose Timer Units with 5 Timers on C161O, one Timer Unit with 3 Timers on C161K
Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)
• Up to 4 MBytes External Address Space for Code and Data
Programmable External Bus Characteristics for Different Address Ranges
Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit Data Bus Width
Four Programmable Chip-Select Signals on C161O, two Chip-Select Signals on C161K
• Idle and Power Down Modes
• Programmable Watchdog Timer
• Up to 63 General Purpose I/O Lines
• Power Supply: the C161K/O can operate from a 5 V or a 3 V power supply
• Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards
• On-Chip Bootstrap Loader
• 80-Pin MQFP Package (0.65 mm pitch)

Pinout

Connection Diagram

Specifications

Parameter	Symbol	Limit Values		Unit	Notes
Parameter	Symbol	Min.	Max.	Unit	Notes
Storage temperature	T_ST	-65	150		-
Junction temperature	T_J	-40	150		under bias
Voltage on V_DD pins with respect to ground (V_SS)	V_DD	-0.5	6.5	V	-
Voltage on any pin with respect to ground (V_SS)	V_IN	-0.5	V_DD + 0.5	V	-
Input current on any pin during overload condition	I_OV	-10	10	mA	-
Absolute sum of all input currents during overload condition	\|I_OV\|	-	\|100\|	mA	-
Power dissipation	P_DISS	-	1.5	W	-

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (V_IN> V_DDor V_IN < V_SS) the voltage on V_DD pins with respect to ground (V_SS) must not exceed the values defined by the absolute maximum ratings.

Description

The architecture of the C161K/O combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. In addition the on-chip memory blocks allow the design of compact systems with maximum performance.

The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C161K/O.

C161O

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