CD22203

Features:

• Central Office Quality
• No Front End Band Splitting Filters Required
• Single, Low Tolerance, 5V Supply
• Detects Either 12 or 16 Standard DTMF Digits
• Uses Inexpensive 3.579545MHz Crystal for Reference
• Excellent Speech Immunity
• Output in Either 4-Bit Hexadecimal Code or Binary Coded 2-of-8
• Synchronous or Handshake Interface
• Three-State Outputs
• Excellent Latch-Up Immunity


Pinout




Specifications

DC Supply Voltage (V_DD)(Referenced to VSS Terminal). . . . . . . . 7V
Power Dissipation
T_A = 25 (Derate above T_A = 25 at 6.25mW/. . . . . . .. . . 65mW
Input Voltage Range
All Inputs Except Analog In . . . . . . . . . . . . .. . . (V_DD +0.5V) to -0.5V
Analog in Voltage Range . . . . . . . . . . .. . . (V_DD +0.5V) to (V_DD -10V)
DC Current into any Input or Output . . . . . . . . . . . . . . . . . . ..±20mA
NOTE: Unused inputs must be connected to V_DD or V_SS as appropriate.


Description

The CD22202 and CD22203 complete dual-tone multiple frequency (DTMF) receivers detect a selectable group of 12 or 16 standard digits. No front-end pre-filtering is needed. The only externally required components are an inexpensive 3.579545MHz TV "colorburst" crystal (for frequency reference) and a bias resistor. Extremely high system density is possible through the use of the clock output of a crystal connected CD22202/CD22203 receiver to drive the time bases of additional receivers. This is a monolithic integrated circuit fabricated with low-power, complementary symmetry CMOS processing. It only requires a single low tolerance power supply.

The CD22202 and CD22203 employ state-of-the-art circuit technology to combine the digital and analog functions on the same CMOS chip using a standard digital semiconductor process. The analog input is preprocessed by 60Hz reject and band splitting filters and then hard limited to provide AGC. Eight Bandpass filters detect the individual tones. The digital post processor times the tone durations and provides
the correctly coded digital outputs. CD22203 Outputs interface directly to standard CMOS circuitry and are three-state enabled to facilitate bus oriented architectures.