CD4033BMS

CD4033BMS consists of a 5 stage Johnson decade counter and an output decoder which converts the Johnson code to a 7 segment decoded output for driving one stage in a numerical display.

CD4033BMS is particularly advantageous in display applications where low power dissipation and/or low package count is important.

CD4033BMS high RESET signal clears the decade counter to its zero count. The CD4033BMS counter is advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. The CD4033BMS CLOCK INHIBIT signal can be used as a negative-edge clock if CD4033BMS clock line is held high. CD4033BMS Antilock gating is provided on the JOHNSON counter, thus assuring proper counting sequence. The CARRY-OUT (Cout) signal completes one cycle every ten CLOCK INPUT cycles and is used to clock the succeeding decade directly in a multi-decade counting chain.

CD4033BMS seven decoded outputs (a, b, c, d, e, f, g) illuminate the proper segments in a seven segment display device used for representing the decimal numbers 0 to 9. The 7 segment outputs go high on selection.