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Part Number: CD74AC175

 

 

 

 

Description: The CD74AC175 and CD74ACT175 are quad D flip-flops with reset that utilize the Harris Advanced CMOS Logic technology. I...


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CD74AC175 General Description


The CD74AC175 and CD74ACT175 are quad D flip-flops with reset that utilize the Harris Advanced CMOS Logic technology. Information at the D input is transferred to the Q and Q outputs on the positive-going edge of the clock pulse. All four flip-flops are controlled by a common clock (CP) and a common reset (MR). Resetting is accomplished by a LOW logic level independent of the clock.

CD74AC175 Maximum Ratings

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . .  . -0.5V to 6V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . .  . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . .. .±50mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . .  .  . .±50mA
DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . .  . .±100mA
 

CD74AC175 Features

• Buffered Inputs
• Typical Propagation Delay
  - 6.4ns at VCC = 5V, TA = 25, CL = 50pF
• Exceeds 2kV ESD Protection MIL-STD-883, Method 3015
• SCR-Latchup-Resistant CMOS Process and Circuit Design
• Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption
• Balanced Propagation Delays
• AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply
• ±24mA Output Drive Current
  - Fanout to 15 FAST™ ICs
  - Drives 50W Transmission Lines

CD74AC175 Connection Diagram

CD74AC175  Connection Diagram

CD74AC175 datasheet

CD74AC175
PDF/DataSheet Download

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