CD74ACT245

Features: • Buffered Inputs• Typical Propagation Delay - 4ns at VCC = 5V, TA = 25oC, CL = 50pF• Exceeds 2kV ESD Protection MIL-STD-883, Method 3015• SCR-Latchup-Resistant CMOS Process and Circuit Design• Speed of Bipolar FAST™/AS/S with Significantly Reduced Pow...

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CD74ACT245 Picture
SeekIC No. : 004311911 Detail

CD74ACT245: Features: • Buffered Inputs• Typical Propagation Delay - 4ns at VCC = 5V, TA = 25oC, CL = 50pF• Exceeds 2kV ESD Protection MIL-STD-883, Method 3015• SCR-Latchup-Resistant CMO...

floor Price/Ceiling Price

Part Number:
CD74ACT245
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/3/28

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Product Details

Description



Features:

• Buffered Inputs
• Typical Propagation Delay - 4ns at VCC = 5V, TA = 25oC, CL = 50pF
• Exceeds 2kV ESD Protection MIL-STD-883, Method 3015
• SCR-Latchup-Resistant CMOS Process and Circuit Design
• Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption
• Balanced Propagation Delays
• AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply
• ±24mA Output Drive Current - Fanout to 15 FAST™ ICs - Drives 50W Transmission Lines



Pinout

  Connection Diagram


Specifications

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . . . . .±100mA



Description

The CD74AC245 and CD74ACT245 are octal-bus transceivers that utilize the Harris Advanced CMOS Logic technology.
They are non-inverting three-state bidirectional transceiverbuffers intended for two-way transmission from "A" bus to "B" bus or "B" bus to "A". The logic level present on the direction input (DIR) determines the data direction. When the output enable input (OE) is HIGH, the outputs are in the highimpedance state.


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