CD74HC7046AEE4

Maximum Input Frequency :
Minimum Input Frequency :
Output Frequency Range :
Number of Circuits : 1
Type : PLL
Supply Voltage - Max : 6 V
Supply Voltage - Min : 2 V
Maximum Operating Temperature : + 125 C
Package / Case : PDIP-16
Packaging : Tube
Minimum Operating Temperature : - 55 C


Features:

• Center Frequency of 18MHz (Typ) at V_CC = 5V,
   Minimum Center Frequency of 12MHz at V_CC = 4.5V
• Choice of Two Phase Comparators
   - Exclusive-OR
   - Edge-Triggered JK Flip-Flop
• Excellent VCO Frequency Linearity
• VCO-Inhibit Control for ON/OFF Keying and for Low
  Standby Power Consumption
• Minimal Frequency Drift
• Zero Voltage Offset Due to Op-Amp Buffer
• Operating Power-Supply Voltage Range
   - VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . .3V to 6V
   - Digital Section . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
• Fanout (Over Temperature Range)
   - Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads
   - Bus Driver Outputs . . . . . . . . . . . . .15 LSTTL Loads
• Wide Operating Temperature Range . . .-55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
   Logic ICs
• HC Types
   - 2V to 6V Operation
   - High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CCat V_CC = 5V
• HCT Types
   - 4.5V to 5.5V Operation
   - Direct LSTTL Input Logic Compatibility,V_IL= 0.8V (Max), V_IH = 2V (Min)
   - CMOS Input Compatibility, I_l1µ A at V_OL, V_OH


Application

• FM Modulation and Demodulation
• Frequency Synthesis and Multiplication
• Frequency Discrimination
• Tone Decoding
• Data Synchronization and Conditioning
• Voltage-to-Frequency Conversion
• Motor-Speed Control
• Related Literature
   - AN8823, CMOS Phase-Locked-Loop Application
     Using the CD74HC/HCT7046A and
     CD74HC/HCT7046A


Pinout




Specifications

DC Supply Voltage, V_CC. . . . . . . . . . . . . . . . . . . . . . . .b-0.5V to 7V
DC Input Diode Current, I_IK
For V_I < -0.5V or V_I > V_CC + 0.5V. . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I_OK
For V_O < -0.5V or V_O > V_CC + 0.5V . . . . . . . . . . . . . . . . . . ..±20mA
DC Output Source or Sink Current per Output Pin, I_O
For V_O > -0.5V or V_O < V_CC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC V_CC or Ground Current, I_CC . . . . . . . . . . . . . . . . . . .  . . .±50mA


Description

The CD74HC7046A and CD74HCT7046A high-speed silicon-gate CMOS devices, specified incompliance with JEDEC Standard No.7A, are phase-locked-loop (PLL) circuits that contain aline arvoltage-controlledo scillator (VCO) ,two-phase comparators (PC1,PC2),and alock detector .A signal input an dacomparator in put are common to each comparator.The lock detector gives a HIGH level at pin1(LD) when the PLLis locked.CD74HC7046AEE4 lock detector capacitor must be connected between pin15(CLD)and pin 8(Gnd). For afrequency range of 100k Hzto10 MHz,the lock detector capacitor should be 1000pF to10pF, respectively.

The signal in put can be directly coupled to large voltage signals, orindirectly coupled (with aseries capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals with in the lin earregi on of the input amplifiers. With apassive low-pass filter,the 7046A for msasecond-oderlooPLL.CD74HC7046AEE4 excellent VCO linear it yi sa chieved by the use of linear op-amp techniques.

Parameters:

Technical/Catalog Information	CD74HC7046AEE4
Vendor	Texas Instruments
Category	Integrated Circuits (ICs)
Type	Phase Lock Loop (PLL)
Voltage - Supply	2 V ~ 6 V
Number of Outputs	4
Input	-
Output	-
Frequency-Max	38MHz
Package / Case	16-DIP (300 mil)
Packaging	Tube
Operating Temperature	-55°C ~ 125°C
Drawing Number	296; 4040049; N; 14, 16, 18, 20
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	CD74HC7046AEE4 CD74HC7046AEE4