Purchase CY2SSTV858-32, In-stock CY2SSTV858-32 From SeekIC.
Part Number: CY2SSTV858-32
Description: The CY2SSTV858-32 is a high-performance, low-skew, low-jitter zero-delay buffer designed to distribute...
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CY2SSTV858-32
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DataSheet
General Description
CY2SSTV858-32 General Description
The CY2SSTV858-32 is a high-performance, low-skew, low-jitter zero-delay buffer designed to distribute differential clocks in high-speed applications. The CY2SSTV858-32 generates ten differential pair clock outputs from one differential pair clock input. In addition, the CY2SSTV857-32 features differential feedback clock outpts and inputs. This allows the CY2SSTV858-32 to be used as a zero delay buffer. When used as a zero delay buffer in nested clock trees, the CY2SSTV857-32 locks onto the input reference and translates with near-zero delay to low-skew outputs.
CY2SSTV858-32 Maximum Ratings
Input Voltage Relative to VSS:...............................VSS 0.3V
Input Voltage Relative to VDDQ or AVDD: .......... VDDQ + 0.3V
Storage Temperature: .............................. 65°C to + 150°C
Operating Temperature:.............................. 40°C to +85°C
Maximum Power Supply: ...............................................3.5V
Input Voltage Relative to VDDQ or AVDD: .......... VDDQ + 0.3V
Storage Temperature: .............................. 65°C to + 150°C
Operating Temperature:.............................. 40°C to +85°C
Maximum Power Supply: ...............................................3.5V
CY2SSTV858-32 Features
• Operating frequency: 60 MHz to 230 MHz
• Supports 400 MHz DDR SDRAM
• 10 differential outputs from one differential input
• Spread-Spectrum-compatible
• Low jitter (cycle-to-cycle): < 75
• Very low skew: < 100 ps
• Power management control input
• High-impedance outputs when input clock < 20 MHz
• 2.6V operation
• Pin-compatible with CDC857-2 and -3
• 48-pin TSSOP and 40 QFN package
• Industrial temperature of 40°C to 85°C
• Conforms to JEDEC DDR specification
• Supports 400 MHz DDR SDRAM
• 10 differential outputs from one differential input
• Spread-Spectrum-compatible
• Low jitter (cycle-to-cycle): < 75
• Very low skew: < 100 ps
• Power management control input
• High-impedance outputs when input clock < 20 MHz
• 2.6V operation
• Pin-compatible with CDC857-2 and -3
• 48-pin TSSOP and 40 QFN package
• Industrial temperature of 40°C to 85°C
• Conforms to JEDEC DDR specification
CY2SSTV858-32 Connection Diagram
CY2030
PDF/DataSheet Download
- Datasheet: CY2030
- File Size: 89675 KB
- Manufacturer: Cypress
- Click here to Download
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CY2SSTV858-32 Relative Products
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The CY2SSTV857-32 is a high-performance, low-skew, low-jitter zero-delay buffer designed to distribute differential clocks in high-speed applications. The CY2SSTV857-32 generates ten differential pair clock outputs from one differential pair clock input. In ...
CY2SSTV857-27
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CY2SSTV855ZC
The CY2SSTV855ZC is a high-performance, very-low-skew, very-low-jitter zero-delay buffer that distributes a differential clock input pair (SSTL_2) to four differential (SSTL_2) pairs of clock outputs and one differential pair of feedback clock outputs. In su...
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