CY7C1324

The CY7C1324 is a 3.3V, 128K by 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay of CY7C1324 from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.

The CY7C1324 allows both interleaved or linear burst sequences, selected by the MODE input pin. A HIGH input on MODE selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input.

A synchronous self-timed write mechanism is provided to simplify the write interface. A synchronous chip of CY7C1324 enable input and an asynchronous output enable input provide easy control for bank selection and output three-state control.