CY7C1340F-100AC

The CY7C1340F-100AC is designed as one kind of 4-Mb (128K x 32) pipelined DCD sync SRAM that all the synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). This device operates from a +3.3V core power supply while all outputs operate with a +3.3V or a +2.5V supply. All inputsand outputs are JEDEC-standard JESD8-5-compatible.

Features of the CY7C1340F-100AC are:(1)"ZZ" Sleep Mode option;(2)JEDEC-standard 100-pin TQFP package and pinout;(3)Asynchronous Output Enable;(4)Synchronous self-timed writes;(5)Separate processor and controller address strobes;(6)Provide high-performance 3-1-1-1 access rate;(7)User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences;(8)Registered inputs and outputs for pipelined operation;(9)Optimal for performance (Double-Cycle deselect) Depth expansion without wait state;(10)128K * 32-bit common I/O architecture.

The absolute maximum ratings of the CY7C1340F-100AC can be summarized as:(1)Storage Temperature:65°C to +150°C;(2)Ambient Temperature with Power Applied: -55°C to +125°C;(3)Supply Voltage on VDD Relative to GND: -0.5V to +4.6V;(4)DC Voltage Applied to Outputs in Three-State: -0.5V to VDDQ+0.5V;(5)DC Input Voltage: -0.5V to VDD+0.5V;(6)Current into Outputs (LOW): 20 mA;(7)Latch -up Current: >200 mA;(8)Static Discharge Voltage: >2001V. If you want to know more information such as the electrical characteristics about the CY7C1340F-100AC, please download the datasheet in www.seekic.com or www.chinaicmart.com.