CY7C1340F

The CY7C1340F SRAM integrates 131,072 x 32 SRAM cellswith advanced synchronous peripheral circuitry and a two-bitcounter for internal burst operation. All synchronous inputs aregated by registers controlled by a positive-edge-triggeredClock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable(CE1), depth-expansion Chip Enables (CE2 and CE3), BurstControl inputs (ADSC, ADSP, andADV), Write Enables(BW[A:D], and BWE), and Global Write (GW). Asynchronousinputs include the Output Enable (OE) and the ZZ pin.

Addresses and chip enables are registered at rising edge ofclock when either Address Strobe Processor (ADSP) orAddress Strobe Controller (ADSC
) are active. Subsequentburst addresses can be internally generated as controlled bythe Advance pin (ADV).

Address, data inputs, and write controls are registered on-chipto initiate a self-timed Write cycle.This part supports Byte Writeoperations (see Pin Descriptions and Truth Table for furtherdetails). Write cycles can be one to four bytes wide ascontrolled by the byte write control inputs. GWactive
LOWcauses all bytes to be written. This device incorporates anadditional pipelined enable register which delays turning off
the output buffers an additional cycle when a deselect isexecuted.This feature allows depth expansion without penal-izing system performance.

The CY7C1340F operates from a +3.3V core power supplywhile all outputs operate with a +3.3V or a +2.5V supply. Allinputsand outputs are JEDEC-standard JESD8-5-compatible..