CY7C1350F

The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelinedBurst SRAM designed specifically to support unlimited trueback-to-back Read/Write oper
ations without the insertion ofwait states. The CY7C1350F is equipped with the advancedNo Bus Latency™ (NoBL™) logic required to enable consec-
utive Read/Write operations with data being transferred onevery clock cycle. This feature dramatically improves thethroughput of the SRAM, especi
ally in systems that requirefrequent Write/Read transitions.

All synchronous inputs pass through input registers controlledby the rising edge of the clock. All data outputs pass throughoutput registers controlled by the rising edge of the clock. Theclock input is qualified by the Clock Enable (CEN) signal,which, when deasserted, suspends operation and extends theprevious clock cycle. Maximum access delay from the clockrise is 2.8 ns (200-MHz device)

Write operations are controlled by the four Byte Write Select(BW[A:D]) and a Write Enable (WE) input. All writes areconducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and anasynchronous Output Enable (OE) provide for easy bankselection and output three-state control. In order to avoid buscontention, the output drivers are synchronously three-statedduring the data portion of a write sequence.