CY7C340

The Cypress Multiple Array Matrix (MAX®)CY7C340 family of EPLDs provides a user-configurable, high-density solution to general- purpose logic integration requirements. With the combination of innovative architecture and state-of-the-art process, the MAX EPLDs CY7C340 offer LSI density without sacrificing speed.

The MAX architecture makes CY7C340 ideal for replacing large amounts of TTL SSI and MSI logic. For example, a 74161 counter utilizes only 3% of the 128 macrocells available in the CY7C342B. Similarly, a 74151 8-to-1 multiplexer consumes less than 1% of the over 1,000 product terms in the CY7C342B. This allows the designer to replace 50 or more TTL packages with just one MAX EPLD. The family comes in a range of densities, shown below. By standardizing on a few MAX CY7C340 building blocks, the designer can replace hundreds of different 7400 series part numbers currently used in most digital systems.

The CY7C340 family is based on an architecture of flexible macrocells grouped together into Logic Array Blocks (LABs). Within the LAB is a group of additional product terms called expander product terms. These expanders are used and shared by the macrocells, allowing complex functions of up to 35 product terms to be easily implemented in a single macrocell. A Programmable Interconnect Array (PIA)CY7C340 globally routes all signals within devices containing more than one LAB. This architecture is fabricated on the Cypress 0.8-micron, double-layer- metal CMOS EPROM process, yielding devices with significantly higher integration, density and system clock speed than the largest of previous generation EPLDs. The CY7C34XB devices are 0.65-micron shrinks of the original 0.8-micron family. The CY7C34XBs offer faster speed bins for CY7C340 in the Cypress MAX family.

The density and performance of the CY7C340 family is accessed using Cypress's Warp2 and Warp3 design software. Warp2 provides state-of-the-art VHDL synthesis for MAX and FLASH370™ at a very low cost. Warp3 is a sophisticated CAE CY7C340 tool that includes schematic capture (ViewDraw) and timing simulation (ViewSim) in addition to VHDL synthesis. Consult the Warp2 and Warp3 datasheets for more information about the development tools.