CY7C4211V

The CY7C42X1V are high-speed, low-power, FIFO memories with clocked read and write interfaces. All are nine bits wide. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multi-
processor interfaces, and communications buffering.

These FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a Free-Running Clock (WCLK) and two Write Enable pins (WEN1 , WEN2/LD ).

When WEN1  is LOW and WEN2/LD  is HIGH, data is written into the FIFO on the rising edge of the WCLK signal. While WEN1 , WEN2/LD  is held active, data is continually written into the FIFO on each WCLK cycle. The output port is controlled in a similar manner by a Free-Running Read Clock (RCLK) and two Read Enable Pins (WEN1 , REN2 ). In addition, the CY7C42X1V has an Output Enable Pin (OE ). The Read (RCLK) and Write (WCLK) clocks may be tied together for single-clock operation or the two clocks may be run indepen- dently for asynchronous read/write applications. Clock frequencies up to 66 MHz are achievable.

Depth expansion is possible using one enable input for system control, while the other enable is controlled by expansion logic to direct the flow of data.