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Description: The 200-MBaud CY7C924DX HOTLink Transceiver is a pointto- point communications building block allowing...


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CY7C924DX General Description


The 200-MBaud CY7C924DX HOTLink Transceiver is a pointto- point communications building block allowing the transfer of data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at speeds ranging between 50 and 200 MBaud. The transmit section accepts parallel data of selectable width and converts it to serial data, while the receiver section accepts serial data and converts it to parallel data of selectable width. Figure 1 illustrates typical connections between two independent host systems and corresponding CY7C924DX parts. As a second generation HOTLink device, the CY7C924DX provides enhanced levels of technology, functionality, and integration over the field-proven CY7B923/933 HOTLink.

The transmit section of the CY7C924DX HOTLink can be configured to accept either 8- or 10-bit data characters on each clock cycle, and stores the parallel data into an internal Transmit FIFO. Data is read from the Transmit FIFO and is encoded using an embedded 8B/10B encoder to improve its serial transmission characteristics. These encoded characters are then serialized and output from two Positive ECL (PECL) compatible differential transmission line drivers at a bit-rate of 10 times the input reference clock.

The receive section of the CY7C924DX HOTLink accepts a serial bit-stream from one of two PECL-compatible differential line receivers and, using a completely integrated PLL Clock Synchronizer, recovers the timing information necessary for data reconstruction. The recovered bit stream is deserialized and framed into characters, 8B/10B decoded, and checked for transmission errors. Recovered decoded characters are reconstructed into either 8- or 10-bit data characters, written to an internal Receive FIFO, and presented to the destination host system.

The integrated 8B/10B encoder/decoder may be bypassed for systems that present externally encoded or scrambled data at the parallel interface. The embedded FIFOs may also be bypassed to create a reference-locked serial transmission link.

For those systems requiring even greater FIFO storage capability, external FIFOs may be directly coupled to the CY7C924DX device through the parallel interface without additional glue-logic.

The TTL parallel I/O interface may be configured as either a FIFO (configurable for UTOPIA emulation or for depth expansion through external FIFOs) or as a pipeline register extender.

The FIFO configurations are optimized for transport of timeindependent (asynchronous) 8- or 10-bit character-oriented data across a link. A Built-In Self-Test (BIST) pattern generator and checker permits at-speed testing of the high-speed serial data paths in both the transmit and receive sections, and across the interconnecting links.

HOTLink devices are ideal for a variety of applications where parallel interfaces can be replaced with high-speed, point-topoint serial links. Some applications include interconnecting workstations, backplanes, servers, mass storage, and video transmission equipment.

CY7C924DX Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. 65°C to +150°C
Ambient Temperature with
Power Applied............................................. 55°C to +125°C
Supply Voltage to Ground Potential ............... 0.5V to +6.5V
DC Voltage Applied to Outputs
in High-Z State.........................................0.5V to VDD+0.5V
Output Current into TTL Outputs (LOW) ......................30 mA
DC Input Voltage ..................................... 0.5V to VDD+0.5V
Static Discharge Voltage...............................................> 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current...........................................................> 200 mA

CY7C924DX Features

• Second-generation HOTLink® technology
• Fibre Channel and ESCON® compliant 8B/10B encoder/decoder
• 10- or 12-bit pre-encoded data path (raw mode)
• 8- or 10-bit encoded data transport (using 8B/10B coding)
• Parity check/generate
• Synchronous or asynchronous TTL parallel interface
• UTOPIA compatible host bus interface
• Embedded/Bypassable 256-character synchronous FIFOs
• Integrated support for daisy-chain and ring topologies
• Domain or individual destination device addressing
• 50- to 200-MBaud serial signaling rate
• Internal PLLs with no external PLL components
• Dual differential PECL serial inputs
• Dual differential PECL serial outputs
• Compatible with fiber-optic modules and copper cables
• Built-In Self-Test (BIST) for link testing
• Link Quality Indicator
• Single +5.0V ±10% supply
• 100-pin TQFP
• 0.35 CMOS technology

CY7C924DX Connection Diagram

CY7C924DX  Connection Diagram

CY7C924DX datasheet

CY7C924DX
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