DM54LS165

  This DM54LS165 device is an 8-bit serial shif tregister which shifts data in the direction of QA toward QH when clocked Parallel-in ac-cess is made available by eight individual direct data inputs which are enabled by a low level at the shiftload input These DM54LS165 registers also feature gated clock inputs and comple-mentary outputs from the eighth bit

  Clocking is accomplished through a 2-input NOR gate per-mitting one input to be used as a clock-inhibt function .Hold-ing either of the clock inputs high inhibits clocking and hold-ing either clock input low with the load input high enables the other clock input The clock-inhibit input should be changed to the high level only while the clock input is high Parallel loading is inhibited as long as the load input is high Data at the parallel inputs are loaded directly into the DM54LS165 regis-ter on a high-to-low transition of the shiftload input regard-less of the logic levels on the clock clock inhibit or serial inputs