DP83266

Features: · Over 9 kBytes of on-chip FIFO· 5 DMA channels (2 Output and 3 Input)· 12.5 MHz to 25 MHz operation· Full duplex operation with through parity· Supports JTAG boundary scan· Real-time Void stripping indicator for bridges·On-chip address bit swapping capability· 32-bit wide Address/Data p...

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DP83266 Picture
SeekIC No. : 004327938 Detail

DP83266: Features: · Over 9 kBytes of on-chip FIFO· 5 DMA channels (2 Output and 3 Input)· 12.5 MHz to 25 MHz operation· Full duplex operation with through parity· Supports JTAG boundary scan· Real-time Void...

floor Price/Ceiling Price

Part Number:
DP83266
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/27

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Product Details

Description



Features:

· Over 9 kBytes of on-chip FIFO
· 5 DMA channels (2 Output and 3 Input)
· 12.5 MHz to 25 MHz operation
· Full duplex operation with through parity
· Supports JTAG boundary scan
· Real-time Void stripping indicator for bridges
·On-chip address bit swapping capability
· 32-bit wide Address/Data path with byte parity
· Programmable transfer burst sizes of 4 or 8 32-bit words
· Receive frame filtering services
· Frame-per-Page mode controllable on each DMA channel
· Demultiplexed Addresses supported on ABus
· New multicast address matching feature
· ANSI X3T9.5 MAC standard defined ring service options
· Supports all FDDI Ring Scheduling Classes (Synchronous, Asynchronous, etc.)
· Supports Individual, Group, Short, Long and External Addressing
· Generates Beacon, Claim, and Void frames
· Extensive ring and station statistics gathering
· Extensions for MAC level bridging
· Enhanced SBus compatibility
· Interfaces to DRAMs or directly to system bus
· Supports frame Header/Info splitting
· Programmable Big or Little Endian alignment



Pinout

  Connection Diagram


Specifications

Symbol Parameter Conditions Min Typ Max Units
VCC Supply Voltage   -0.5   7.0 V
DCIN Input Voltage   -0.5   VCC +0.5 V
DCOUT Output Voltage   -0.5   VCC + 0.5 V
TSTG Storage Temperature   -65   150
TL Lead Temperature Soldering, 10 Sec.
(IR or Vapor)
(Phase Reflow)
    230
  ESD Protection   2000     V



Description

The DP83266 Media Access Controller and System Interface (MACSI) implements the ANSI X3T9.5 Standard Media Access Control (MAC) protocol for operation in an FDDI token ring and provides a comprehensive System Interface.

The MACSI device DP83266 transmits, receives, repeats, and strips tokens and frames. DP83266 produces and consumes optimized data structures for efficient data transfer. Full duplex architecture with through parity allows diagnostic transmission and self testing for error isolation and point-to-point connections. The MACSI device DP83266 includes the functionality of both the DP83261 BMACTM device and the DP83265 BSI-2TM device with additional enhancements for higher performance and reliability.


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