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Part Number: DP83858
Description: The DP83858 100 Mb/s TX/T4 Repeater Interface Controller, known as 100RIC8, is designed specifically to meet the nee...


Description: The DP83858 100 Mb/s TX/T4 Repeater Interface Controller, known as 100RIC8, is designed specifically to meet the nee...
The DP83858 100 Mb/s TX/T4 Repeater Interface Controller, known as 100RIC8, is designed specifically to meet the needs of today's high speed Ethernet networking systems.
The DP83858 is fully compatible with the IEEE 802.3 repeater's clause 27. This device is targeted at low port count managed and unmanaged repeater applications. The DP83858 supports up to eight 100 Mb/s links with its network interface ports. The 100RIC8 can be configured to be used with either 100BASE-TX or 100BASE-T4 PHY technologies. Larger repeaters may be constructed by cascading DP83858s together using the built-in Inter Repeater bus.
In conjunction with a DP83856 100 Mb/s Repeater Information Base device, a DP83858 based repeater becomes a managed entity that is compatible with IEEE 802.3u (clause 30), collecting and providing an easy interface to all the required network statistics.
Supply Voltage (Vdd) -0.5 V to 7.0V
Supply voltage (Vdd) 5 volts + 5%
DC Input Voltage (Vin) -0.5 V to Vcc + 0.5 V
Ambient Temperature (Ta) 0 to 70c
DC Output Voltage (Vout) -0.5 V to Vcc + 0.5V
Storage Temperature Range (Tstg) -65c to 150c
Power Dissipation (Pd) 1.575 W
Lead Temp (Tl) (soldering 10-sec) 260c
ESD Rating 2.0KV
(Rzap = 1.5k, Czap = 120pF)
· IEEE 802.3u repeater and management compatible
· Supports Class II TX translational repeater and Class I T4 repeater
· Supports 8 network connections (ports)
· Up to 31 repeater chips cascadable for larger hub applications-- may use DP83858 in conjunction with DP83850 100RIC (12 ports per chip)
· Separate jabber and partition state machines for each port
· Management interface to DP83856 allows all repeater MIBs to be maintained
· Large per-port management counters - reduces management CPU overhead
· On-chip elasticity buffer for PHY signal re-timing to the DP83858 clock source
· Serial register interface - reduces cost
· Physical layer device control/status access available via the serial register interface
· Detects repeater identification errors
· 132 pin PQFP package
DP83858
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