DS1004

Features: · All-silicon timing circuit· Five equally delayed clock phases per input· Precise tap-to-tap delay tolerances of ±0.5, ±0.75, or ±1 ns· Input-to-tap 1 delay of 5 ns· Delay tolerances of ±1.5 ns over temperature and voltage · Leading and trailing edge precision preserves the input symmet...

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DS1004 Picture
SeekIC No. : 004328370 Detail

DS1004: Features: · All-silicon timing circuit· Five equally delayed clock phases per input· Precise tap-to-tap delay tolerances of ±0.5, ±0.75, or ±1 ns· Input-to-tap 1 delay of 5 ns· Delay tolerances of ±...

floor Price/Ceiling Price

Part Number:
DS1004
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/24

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Product Details

Description



Features:

· All-silicon timing circuit
· Five equally delayed clock phases per input
· Precise tap-to-tap delay tolerances of ±0.5, ±0.75, or ±1 ns
· Input-to-tap 1 delay of 5 ns
· Delay tolerances of ±1.5 ns over temperature and voltage
· Leading and trailing edge precision preserves the input symmetry
· CMOS design with TTL compatibility
· Standard 8-pin DIP and 150 mil 8-pin SOIC
· Vapor phase, IR and wave solderable
· Available in Tape and Reel



Pinout

  Connection Diagram


Specifications

Voltage on Any Pin Relative to Ground       -1.0V to +7.0V
Operating Temperature                              0°C to 70°C
Storage Temperature                         -55°C to +125°C
Soldering Temperature                  260°C for 10 seconds
Short Circuit Output Current               50 mA for 1 second



Description

The DS1004 is a 5-tap all silicon delay line which can provide 2, 3, 4, or 5 ns tap-to-tap delays within a standard part family. The device is Dallas Semiconductor's fastest 5-tap delay line. It is available in a standard 8-pin DIP and 150 mil 8-pin mini-SOIC.The  DS1004 features precise leading and trailing edge accuracies and has the inherent reliability of an all-silicon delay line solution.

The DS1004 is specified for tap-to-tap tolerances as shown in Table 1. Each device has a minimum inputto- tap 1 delay of 5 ns. Subsequent taps (taps 2 through 5) are precisely delayed by 2, 3, 4, or 5 ns. See Table 1 for details. Tolerance over temperature and voltage is ±1.5 ns. Nominal tap-to-tap tolerances range from ±0.5 ns to ±1.0 ns. Each output is capable of driving up to 10 LS loads.

For customers needing non-standard delay values, the Late Package Program (LPP) is available. Customers may contact Dallas Semiconductor at (972) 3714348 for further details.


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