EL4585C

. 36 MHz general purpose PLL
. 8FSC timing (Use the EL4584 for4FSC )
. Compatible with EL4583C Sync Separator
. VCXO Xtal or LC tank oscillator
. <2nS jitter (VCXO)
. User-controlled PLL capture and lock
. Compatible with NTSC and PAL TV formats
. 8 pre-programmed popular TV scan rate clock divisors
. Single 5V low current operation

The EL4585C is a PLL (Phase Lock Loop) sub system designed for video applications but also suitable for general purpose use up to 36 MHz In a video application this device generates a TTLCMOS compatible Pixel Clock (Clk Out) which is a multi- ple of the TV Horizontal scan rate and phase locked to it

The EL4585C reference signal is a horizontal sync signal TTLCMOS format which can be easily derived from an analog composite video signal with the EL4583 Sync Separator An input signal to ''coast'' is provided for applications where periodic distur- bances are present in the reference video timing such as VTR head switching The Lock detector output indicates correct lock

The EL4585C divider ratio is four ratios for NTSC and four similar ratios for the PAL video timing standards by external selection of three control pins These four ratios have been selected for com- mon video applications including 8 F 6F 27 MHz (CCIR SC SC 601 format) and square picture elements used in some worksta- tion graphics To generate 4 F 3F 135 MHz (CCIR 601 SC SC format) etc use the EL4584 which does not have the addition- al divide by 2 stage of the EL4585

For applications where these frequencies are inappropriate or for general purpose PLL applications the internal divider EL4585C can be by passed and an external divider chain used