EP1C12F256N

The EP1C12F256N belongs to the Cyclone FPGA (Field Programmable Gate Array) Family. It has 12,060 LEs, 52 M4K RAM blocks (128 * 36 bits), 239,616 total RAM bits, 2 PLLs and 249 maximum user I/O pins. It is based on a 1.5-V, 0.13-m, all-layer copper SRAM process. It is a cost-effective solution for data-path applications.

There are some features of EP1C12F256N as follows. (1)supports configuration through low-cost serial configuration device. (2)support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards. (3)support for 66-MHz, 32-bit PCI standard. (4)low speed (311 Mbps) LVDS I/O support. (5)up to two PLLs per device provide clock multiplication and phase shifting. (6)up to eight global clock lines with six clock resources available per logic array block (LAB) row. (7)support for external memory, including DDR SDRAM (133 MHz), FCRAM, and single data rate (SDR) SDRAM. (8)support for multiple intellectual property (IP) cores, including Altera MegaCore functions and Altera Megafunctions Partners Program (AMPPSM) megafunctions.

What comes next is about the absolute maximum ratings of EP1C12F256N. (1)the VCCINT (Supply voltage with respect to ground) is from -0.5 to 2.4 V. (2)the VCCIO (Supply voltage with respect to ground) is from -0.5 to 4.6 V. (3)the VI (DC input voltage) is from -0.5 to 4.6 V. (4)the IOUT (DC output current, per pin) is from -25 to 25 mA. (5)the TSTG (Storage temperature, no bias) is from -65 to 150. (6)the TAMB (Ambient temperature Under bias) is from -65 to 135. (7)the TJ (Junction temperature ,BGA packages under bias) is 135.