MOSFET Dual PCh Digital
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Transistor Polarity : | P-Channel | Drain-Source Breakdown Voltage : | - 20 V | ||
Gate-Source Breakdown Voltage : | +/- 12 V | Continuous Drain Current : | 0.5 A | ||
Resistance Drain-Source RDS (on) : | 780 mOhms | Configuration : | Dual | ||
Maximum Operating Temperature : | + 150 C | Mounting Style : | SMD/SMT | ||
Package / Case : | SC-70-6 | Packaging : | Reel |
Symbol |
Parameter |
Ratings |
Units |
VDSS | Drain-Source Voltage |
-20 |
V |
VGS | Gate-Source Voltage |
±12 |
V |
ID | Drain Current Continuous (Note 1) Pulsed |
-0.5 |
A
|
-1.8 | |||
PD | Power Dissipation for Single Operation (Note 1) |
0.3 |
W |
TJ, TSTG | Operating and Storage Temperature |
-55 to 175 |
Notes:
1. RJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RJC is guaranteed by design while RJA is determined by the user's board design. RJA = 415°C/W when mounted on a minimum pad .
These FDG6318P dual P-Channel logic level enhancement mode MOSFET are produced using Fairchild Semiconductor's advanced PowerTrench process that has been especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETS.
Technical/Catalog Information | FDG6318P |
Vendor | Fairchild Semiconductor |
Category | Discrete Semiconductor Products |
Mounting Type | Surface Mount |
FET Polarity | 2 P-Channel (Dual) |
Drain to Source Voltage (Vdss) | 20V |
Current - Continuous Drain (Id) @ 25° C | 500mA |
Rds On (Max) @ Id, Vgs | 780 mOhm @ 500mA, 4.5V |
Input Capacitance (Ciss) @ Vds | 83pF @ 10V |
Power - Max | 300mW |
Packaging | Tape & Reel (TR) |
Gate Charge (Qg) @ Vgs | 1.2nC @ 4.5V |
Package / Case | SC-70-6, SC-88, SOT-323-6, SOT-363 |
FET Feature | Logic Level Gate |
Lead Free Status | Lead Free |
RoHS Status | RoHS Compliant |
Other Names | FDG6318P FDG6318P |