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MFG:FAIRC Package Cooled:TO-251(IPAK) D/C:09+


Part Number: FQU3N50C
MFG: FAIRC
Package Cooled: TO-251(IPAK)
D/C: 09+
Description: These P-Channel enhancement mode power field ...
MFG:FAIRC Package Cooled:TO-251(IPAK) D/C:09+


MFG: FAIRC
Package Cooled: TO-251(IPAK)
D/C: 09+
Description: These P-Channel enhancement mode power field ...
These P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, planar stripe, DMOS technology.
This advanced technology is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand a high energy pulse in the avalanche and commutation modes. These devices are well suited for electronic lamp ballasts based on the complementary half bridge topology.namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" />
|
Symbol |
Parameter |
FQD3N50C/FQU3N50C |
Units | ||
|
VDSS |
Drain-Source Voltage |
500 |
V | ||
|
ID |
Drain Current |
- Continuous (TC =25°C) |
2.5 |
A | |
|
|
- Continuous (TC = 100°C) |
1.5 |
A | ||
|
IDM |
Drain Current Pulsed (Note 1) |
10 |
A | ||
|
VGSS |
Gate-Source Voltage |
± 30 |
V | ||
|
EAS |
Single Pulsed Avalanche Energy (Note 2) |
200 |
mJ | ||
|
IAR |
Avalanche Current (Note 1) |
2.5 |
A | ||
|
EAR |
Repetitive Avalanche Energy (Note 1) |
3.5 |
mJ | ||
|
d v/dt |
Peak Diode Recovery dv/dt (Note 3) |
4.5 |
V/ns | ||
|
PD |
Power Dissipation (TC = 25°C) |
35 |
W | ||
|
Operating and |
-55 to +150 |
°C | |||
|
TJ, TSTG |
Maximum lead temperature for soldering purposes, |
300 |
°C | ||
FQU3N50C
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