Purchase GAL20LV8, In-stock GAL20LV8 From SeekIC.
Part Number: GAL20LV8
Description: The GAL20LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance availa...
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GAL20LV8
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DataSheet
General Description
GAL20LV8 General Description
The GAL20LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL20LV8D is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently.
The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configurations possible with the GAL20LV8D are the PAL architectures listed in the table of the macrocell description section. GAL20LV8D devices are capable of emulating any of these PAL architectures with full function/fuse map compatibility.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
GAL20LV8 Maximum Ratings
Supply voltage VCC ................................... 0.5 to +4.6V
Input voltage applied ................................ 0.5 to +5.6V
I/O voltage applied ................................... 0.5 to +4.6V
Off-state output voltage applied ............... 0.5 to +4.6V
Storage Temperature ................................. 65 to 150
Ambient Temperature with
Power Applied ......................................... 55 to 125
1.Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to
the device. These are stress only ratings and functional operation of the device at these or at any other
conditions above those indicated in the operational sections of this specification is not implied (while
programming, follow the programming specifications).
Input voltage applied ................................ 0.5 to +5.6V
I/O voltage applied ................................... 0.5 to +4.6V
Off-state output voltage applied ............... 0.5 to +4.6V
Storage Temperature ................................. 65 to 150
Ambient Temperature with
Power Applied ......................................... 55 to 125
1.Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to
the device. These are stress only ratings and functional operation of the device at these or at any other
conditions above those indicated in the operational sections of this specification is not implied (while
programming, follow the programming specifications).
GAL20LV8 Features
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
- 3.5 ns Maximum Propagation Delay
- Fmax = 250 MHz
- 2.5 ns Maximum from Clock Input to Data Output
- UltraMOS® Advanced CMOS Technology
- TTL-Compatible Balanced 8mA Output Drive
• 3.3V LOW VOLTAGE 20V8 ARCHITECTURE
- JEDEC-Compatible 3.3V Interface Standard
- 5V Compatible Inputs
• ACTIVE PULL-UPS ON ALL PINS
• E2 CELL TECHNOLOGY
- Reconfigurable Logic
- Reprogrammable Cells
- 100% Tested/100% Yields
- High Speed Electrical Erasure (<100ms)
- 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs
- Programmable Output Polarity
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
- 100% Functional Testability
• APPLICATIONS INCLUDE:
- Glue Logic for 3.3V Systems
- DMA Control
- State Machine Control
- High Speed Graphics Processing
- Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
- 3.5 ns Maximum Propagation Delay
- Fmax = 250 MHz
- 2.5 ns Maximum from Clock Input to Data Output
- UltraMOS® Advanced CMOS Technology
- TTL-Compatible Balanced 8mA Output Drive
• 3.3V LOW VOLTAGE 20V8 ARCHITECTURE
- JEDEC-Compatible 3.3V Interface Standard
- 5V Compatible Inputs
• ACTIVE PULL-UPS ON ALL PINS
• E2 CELL TECHNOLOGY
- Reconfigurable Logic
- Reprogrammable Cells
- 100% Tested/100% Yields
- High Speed Electrical Erasure (<100ms)
- 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs
- Programmable Output Polarity
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
- 100% Functional Testability
• APPLICATIONS INCLUDE:
- Glue Logic for 3.3V Systems
- DMA Control
- State Machine Control
- High Speed Graphics Processing
- Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
GAL20LV8 Connection Diagram
GAL20LV8
PDF/DataSheet Download
- Datasheet: GAL20LV8
- File Size: 291832 KB
- Manufacturer: LATTICE [Lattice Semiconductor]
- Click here to Download
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