GS8150V18

Because GS8150V18/36A are synchronous devices, address data inputs and read/write control inputs are captured on the rising edge of the input clock. Write cycles are internally selftimed and initiated by the rising edge of the clock input. This eature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.

GS8150V18/36A support pipelined reads utilizing a risingedge- triggered output register. They also utilize a Dual Cycle Deselect (DCD) output deselect protocol.
GS8150V18/36A are implemented with high performance HSTL technology and are packaged in a 119-bump BGA.