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Part Number: GS9020

 

 

Package Cooled: QFP

D/C: 05/06+

Description: The GS9020 is specifically designed to deserialize SMPTE 259M serial digital signals. The inclusion of...


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GS9020 General Description


The GS9020 is specifically designed to deserialize SMPTE 259M serial digital signals. The inclusion of Error Detection and Handling (EDH) ensures the integrity of the data being received from the serial digital interface (SDI). Internal 75Ω termination resistors allow INTERLINX™ seamless connection with the GS9035 Reclocker or the GS9025 eceiver, thus providing a complete, high performance, digital video input processor with EDH, digital sync signal generation, and other system features.

The GS9020 also includes a parallel to serial converter and NRZI scrambler to provide re-serialized, EDH compliant data output. The EDH core implements EDH insertion and extraction according to SMPTE RP-165. This core also generates noise immune timing signals such as horizontal sync, vertical blanking, field ID and ancillary data identification. It also provides many system features such as a FIFO reset pulse (which can be programmed to coincide with either EAV or SAV), TRS-ID and ANC header cor rection, user controlled output blanking and ITU-R-601 output clipping. The GS9020 has an I²C (Inter-Integrated Circuit, I²C is a registered Trademark of Philips) serial interface bus and an 8-bit parallel port for external access to all error flags and device configuration bits.

GS9020 Maximum Ratings

PARAMETER                                                                     VALUE
Supply Voltage                                                 -0.3V to 6.0V
Input Voltage Range (any input)                     -0.3 to VDD +0.3V
Operating Temperature Range                         0°C to 70°C
Storage Temperature                                       -55°C to 150°C
Lead Temperature (soldering, 10 sec)              260°C

GS9020 Features

• fully compatible with SMPTE 259M
• auto-standard operation to 540MHz
• embedded EDH and data processing core
• selectable loop through or re-serialized EDHprocessed serial output
• noise immune HVF timing signal outputs
• configurable FIFO reset pulse for clearing downstream FIFOs
• ANC header and TRS-ID correction for all standards
• user controlled output blanking
• ITU-R-601 output clipping for active picture area
• ancillary data indication
• low system power
• selectable I²C interface or 8-bit parallel port for access to EDH flags and device configuration bits
• EDH flags also available on dedicated pins
• seamless flag mapping to GS9021 EDH coprocessor
• 80 pin LQFP APPLICATIONS

GS9020 Typical Application

SMPTE 259M serial digital receiver for composite and component standards including 4:4:4:4 at 540Mb/s with EDH processing; Noise immune digital sync and timing generation; Cost effective EDH insertion and checking for serial routing and distribution applications.

GS9020 Connection Diagram

GS9020  Connection Diagram

GS9020 datasheet

GS9020
PDF/DataSheet Download

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