GTLP16616

The GTLP16616 is a 17-bit registered bus transceiver thatprovides TTL to GTLP signal level translation. It allows fortransparent, latched and clocked modes of data flow andprovides a buffered GTLP (CLKOUT) clock output from theTTL CLKAB. The device provides a high speed interfacebetween cards operating at TTL logic levels and a back-plane operating at GTLP logic levels. High speed back-plane operation is a direct result of GTLP's reduced outputswing (<1V), reduced input threshold levels and outputedge rate control. The edge rate control minimizes bus set-tling time. GTLP is a Fairchild Semiconductor derivative ofthe Gunning Transceiver logic (GTL) JEDEC standardJESD8-3.

Fairchild's GTLP has internal edge-rate control and is pro-cess, voltage, and temperature (PVT) compensated. Itsfunction is similar to BTL and GTL but with different outputlevels and receiver threshold. GTLP output LOW level istypically less than 0.5V, the output level HIGH is 1.5V andthe receiver threshold is 1.0V.