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GTLP16T1655

Features: Bidirectional interface between GTLP and LVTTL logiclevels Variable Edge Rate Control pin to select desired edgerate on the GTLP backplane (VERC) Partitioned as two 8-Bit transceivers with individual latchtiming and output control but with a common clock. Power up/down high impedance fo...

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SeekIC No. : 004357117 Detail

GTLP16T1655: Features: Bidirectional interface between GTLP and LVTTL logiclevels Variable Edge Rate Control pin to select desired edgerate on the GTLP backplane (VERC) Partitioned as two 8-Bit transceivers with...

GTLP16T1655 Data Sheet

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Part Number:
GTLP16T1655
Supply Ability:
5000

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  • 1~5000
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  • 15 Days
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Product Details

Description



Features:

 Bidirectional interface between GTLP and LVTTL logiclevels
  Variable Edge Rate Control pin to select desired edgerate on the GTLP backplane (VERC)
  Partitioned as two 8-Bit transceivers with individual latchtiming
     and output control but with a common clock.
  Power up/down high impedance for live insertion.
  External pin to pre-condition I/O capacitance to highate
  Bus-hold data inputs on the A-Port eliminates the needfor
     external pull-up resistors on unused inputs
  LVTTL compatible driver and control inputs
  Flow through pinout optimizes PCB layout
  Open drain on GTLP to support wired-or connection
  A Port source/sink −24 mA/+24 mA
  B Port sink +100mA
  D-type flip-flop, latch and transparent data paths
  −40 to 85 Temperature capability
  Available in TSSOP


Pinout

Connection Diagram


Specifications

Supply Voltage (VCC).................... −0.5V to +4.6V
DC Input Voltage (VI)........... .......  −0.5V to +4.6V
DC Output Voltage (VO)
Outputs 3-STATE ...........................−0.5V to +4.6V
Outputs Active (Note 5) ................−0.5V to + 4.6V
DC Output Sink Current into
A Port IOL.................................................... 48 mA
DC Output Source Current from
A Port IOH ................................................ .−48 mA
DC Output Sink Current
into B Port in the LOW State, IOL
(Note 6) ..................................................  ..200 mA
DC Input Diode Current (IIK)
VI< 0V ....................................................... −50 mA
DC Output Diode Current (IOK)
VO < 0V ......................................................−50 mA
VO > VCC ....................................................+50 mA
ESD Rating >2000V
Storage Temperature (TSTG) ........ −65 to +150


Description

The GTLP16T1655 is a 16-bit universal bus transceiverthat provides LVTTL to GTLP signal level translation. Itallows for transparent, latched and clocked modes of datatransfer. The GTLP16T1655 provides a high speed interfacebetween cards operating at LVTTL logic levels and a back-plane operating at GTLP logic levels. High speed back-plane operation is a direct result of GTLP's reduced outputswing (<1V), reduced input threshold levels and outputedge rate control. The edge rate control minimizes bus set-tling time. GTLP is a Fairchild Semiconductor derivative ofthe Gunning Transceiver Logic (GTL) JEDEC standardJESD8-3.

Fairchild's GTLP GTLP16T1655 has internal edge-rate control and is pro-cess, voltage, and temperature (PVT) compensated. Itsfunction is similar to BTL and GTL but with different outputlevels and receiver threshold. GTLP GTLP16T1655 output LOW level istypically less than 0.5V, the output level HIGH is 1.5V andthe receiver threshold is 1.0V.




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