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H8S2318

Features: The features of the bus controller are listed below.• Manages external address space in area units - In advanced mode, manages the external space as 8 areas of 2 Mbytes - Bus specifications can be set independently for each area - Burst ROM interfaces can be set• Basic bus in...

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H8S2318: Features: The features of the bus controller are listed below.• Manages external address space in area units - In advanced mode, manages the external space as 8 areas of 2 Mbytes - Bus specifi...

H8S2318 Data Sheet

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Part Number:
H8S2318
Supply Ability:
5000

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Product Details

Description



Features:

The features of the bus controller are listed below.
• Manages external address space in area units
   -  In advanced mode, manages the external space as 8 areas of 2 Mbytes
   -  Bus specifications can be set independently for each area
   -  Burst ROM interfaces can be set
• Basic bus interface
   - Chip select signals (CS0 to CS7) can be output for areas 0 to 7
   - 8-bit access or 16-bit access can be selected for each area
   - 2-state access or 3-state access can be selected for each area
   - Program wait states can be inserted for each area
• Burst ROM interface
   - Burst ROM interface can be set for area 0
   - Selection of 1- or 2-state burst access
• Idle cycle insertion
   - An idle cycle can be inserted in case of external read cycles in different areas
   - An idle cycle can be inserted in case of an external write cycle immediately after an external read cycle
• Bus arbitration function
   - Includes a bus arbiter that arbitrates bus mastership between the CPU and DTC
• Other features
   - External bus release function


Pinout

Connection Diagram


Specifications

Item
Symbol
Value
Unit
Power supply voltage
VCC
0.3 to +4.3
V
Input voltage (except port 4)
Vin
0.3 to VCC +0.3
V
Input voltage (port 4)
Vin
0.3 to AV +0.3
V
Reference power supply voltage
Vr e f
0.3 to AVCC +0.3
V
Analog power supply voltage
AVCC
0.3 to +4.3
V
Analog input voltage
VAN
0.3 to AVCC +0.3
V
Operating temperature
Topr
Regular specifications: 20 to +75
Wide-range specifications: 40 to +85
Storage Temperature
TST
55 to +125
Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded.


Description

The H8S/2319 and H8S/2318 Series have an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily.

The  H8S/2319 and H8S/2318 Series  bus controller also has a bus arbitration function, and controls the operation of the internal bus masters-the CPU and data transfer controller (DTC).




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