H8S_2166_1219915

• Upward-compatibility with H8/300 and H8/300H CPUs
   - Can execute H8/300 CPU and H8/300H CPU object programs
• General-register architecture
   - Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers
• Sixty-five basic instructions
   - 8/16/32-bit arithmetic and logic instructions
   - Multiply and divide instructions
   - Powerful bit-manipulation instructions
• Eight addressing modes
   - Register direct [Rn]
   - Register indirect [@ERn]
   - Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
   - Register indirect with post-increment or pre-decrement [@ERn+ or @ERn]
   - Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
   - Immediate [#xx:8, #xx:16, or #xx:32]
   - Program-counter relative [@(d:8,PC) or @(d:16,PC)]
   - Memory indirect [@@aa:8]
• 16 Mbytes address space
   -Program: 16 Mbytes
   -Data: 16 Mbytes
• High-speed operation
   -All frequently-used instructions are executed in one or two states
   -8/16/32-bit register-register add/subtract: 1 state
   -8 * 8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B)
   -16 ÷ 8-bit register-register divide: 12 states (DIVXU.B)
   -16 * 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W)
   -32 ÷ 16-bit register-register divide: 20 states (DIVXU.W)
Rev. 3.00, 03/04, page 16 of 830
• Two CPU operating modes
   - Normal mode*
   - Advanced mode
Note: * Not available in this LSI.
• Power-down state
   - Transition to power-down state by
   - SLEEP instruction Selectable CPU clock speed