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Features: • Maximum 16-pulse input/output A total of 16 timer general registers (TGRs) are provided (four each for channels 0 and 3,and two each for channels 1, 2, 4, and 5), each of which can be set independently as anoutput compare/input capture register TGRC and TGRD for c...

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SeekIC No. : 004357958 Detail

H8S/2643: Features: • Maximum 16-pulse input/output A total of 16 timer general registers (TGRs) are provided (four each for channels 0 and 3,and two each for channels 1, 2, 4, and 5), each of w...

H8S/2643 Data Sheet

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Part Number:: H8S/2643
Supply Ability:: 5000

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1~5000

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Negotiable

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15 Days

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Upload time: 2024/4/26

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Product Details

Description

Features:

• Maximum 16-pulse input/output
 A total of 16 timer general registers (TGRs) are provided (four each for channels 0 and 3,
and two each for channels 1, 2, 4, and 5), each of which can be set independently as an
output compare/input capture register
 TGRC and TGRD for channels 0 and 3 can also be used as buffer registers
• Selection of 8 counter input clocks for each channel
• The following operations can be set for each channel
 Waveform output at compare match: Selection of 0, 1, or toggle output
 Input capture function: Selection of rising edge, falling edge, or both edge detection
 Counter clear operation: Counter clearing possible by compare match or input capture
 Synchronous operation: Multiple timer counters (TCNT) can be written to simultaneously
 Simultaneous clearing by compare match and input capture possible
 Register simultaneous input/output possible by counter synchronous operation
 PWM mode: Any PWM output duty can be set
 Maximum of 15-phase PWM output possible by combination with synchronous operation
• Buffer operation settable for channels 0 and 3
 Input capture register double-buffering possible
 Automatic rewriting of output compare register possible
• Phase counting mode settable independently for each of channels 1, 2, 4, and 5
 Two-phase encoder pulse up/down-count possible
• Cascaded operation
 Channel 2 (channel 5) input clock operates as 32-bit counter by setting channel 1 (channel 4) overflow/underflow
• Fast access via internal 16-bit bus
 Fast access is possible via a 16-bit bus interface
• 26 interrupt sources
 For channels 0 and 3, four compare match/input capture dual-function interrupts and one
overflow interrupt can be requested independently
 For channels 1, 2, 4, and 5, two compare match/input capture dual-function interrupts, one overflow interrupt, and one underflow interrupt can be requested independently
• Automatic transfer of register data
 Block transfer, 1-word data transfer, and 1-byte data transfer possible by data transfer controller (DTC) or DMA controller (DMAC)
• Programmable pulse generator (PPG) output trigger can be generated
 Channel 0 to 3 compare match/input capture signals can be used as PPG output trigger
• A/D converter conversion start trigger can be generated
 Channel 0 to 5 compare match A/input capture A signals can be used as A/D converter conversion start trigger
• Module stop mode can be set
 As the initial setting, TPU operation is halted. Register access is enabled by exiting module stop mode.

Specifications

Item	Symbol	Value	Unit
Power supply voltage Input voltage (XTAL, EXTAL, OSC1, OSC2) Input voltage (ports 4 and 9) Input voltage (except XTAL, EXTAL, OSC1, OSC2, ports 4 and 9) Reference voltage Analog power supply voltage Analog input voltage Operating temperature Storage temperature	VCC PLLVCC PVCC Vin Vin Vin Vref AVCC VAN Topr Tstg	0.3 to +4.3 0.3 to +7.0 0.3 to VCC +0.3 0.3 to AVCC +0.3 0.3 to PVCC +0.3 0.3 to AVCC +0.3 0.3 to +7.0 0.3 to AVCC +0.3 Regular specifications: 20 to +75 Wide-range specifications: 40 to +85 55 to +125	V V V V V V V V °C °C °C

Caution: Permanent damage to the chip may result if absolute maximum rating are exceeded.

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H8S/2643

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