HEF4520B

The HEF4520B is a dual 4-bit internally synchronous binary counter. The HEF4520B counter has an active HIGH clock input (CP₀) and an active LOW clock input (CP₁), buffered outputs from all four bit positions (O₀ to O₃) and an active HIGH overriding asynchronous master reset input (MR).

The HEF4520B counter advances on either the LOW to HIGH transition of the CP₀ input if CP₁ is HIGH or the HIGH to LOW transition of the CP₁ input if CP₀ is low. Either CP₀ or CP₁ may be used as the clock input to the counter and the other clock input may be used as a clock enable input. A HIGH on MR resets the counter (O₀ to O₃ = LOW) independent of CP₀, CP₁.Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.