HM-6561

Features:

• This Circuit is Processed in Accordance to MIL-STD- 883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1.
• Low Power Standby . . . . . . . . . . . . . . . . . . . . 50mW Max
• Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 200ns Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min
• TTL Compatible Input/Output
• High Output Drive - 1 TTL Load
• On-Chip Address Registers
• Common Data In/Out
• Three-State Output
• Easy Microprocessor Interfacing


Pinout




Specifications

Supply Voltage . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . .+7.0V
Input or Output Voltage. . . . . . . . . . . . . . . GND -0.3V to V_CC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1


Description

The HM-6561/883 is a 256 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high performance and low power operation.

On-chip latches are provided for address and data outputs allowing efficient interfacing with microprocessor systems. The data output buffers of HM-6561/883  can be forced to a high impedance state for use in expanded memory arrays. The data inputs and outputs are multiplexed internally for common I/O bus compatibility.

The HM-6561/883 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature.